Scalable THz Network-On-Chip Architecture for Multichip Systems

Table 3

The comparison of the proposed THz multichip system with the related works.

Reference	Number of chips	Intrachip configuration	Interchip configuration	Total peak bandwidth per chip (Gbps/chip)	Average packet latency (cycles) (PIR = 0.01)
[3]	4	Small world	Token	640	200
[24]	4 processing chips + 4 in-package DRAM	Small world	Control packet based-MAC	208	180
[26]	9	Small world	Phase-based communication	1340	25
This work	16	Small world	OFDMA	1638	79