Research Article  Open Access
FPGA Control Implementation of a GridConnected CurrentControlled VoltageSource Inverter
Abstract
The full control system of a gridconnected currentcontrolled voltagesource inverter (CCVSI) has been designed and implemented on a fieldprogrammable gate array (FPGA). Various control functions and implementation methods are described and discussed. The practical viability of the system is evaluated in an experimental setup, where a VSI supplies 30 kW into the local grid at 400 V. A phaselocked loop (PLL) is used for grid phase tracking and evaluated for simulated abnormal grid conditions. Power factor is kept at unity, and the implemented control system is stressed with step responses in the supplied active power. A movingaverage filter is implemented to reduce the effects of noise and harmonics on the current control loops. A coupling between active and reactive power flow is observed for the step responses but may be ignored in this context. The proposed system is fully comparable with more conventional microprocessorbased control systems.
1. Introduction
The voltage source inverter (VSI) has become increasingly used for grid connection of renewable energy sources, such as wind power turbines or solar cells. Improved ratings in semiconductor components like the insulatedgate bipolar transistor (IGBT) are gaining market for more and more powerful applications where only the thyristorcontrolled currentsource converter has been used earlier. The VSI is dominating the market of distributed generation and may be controlled by either voltage or current feedback. Currentcontrol (CC) is favoured due to its excellent dynamic characteristics and its inherent overcurrent protection. There are three major groups of currentcontrol modulations for VSIs, namely, hysteresis control [1], predictive current control [2], and ramp comparison [3]. A survey on currentcontrol methods is presented in [4].
Depending on the control strategy, the power converter control system has traditionally been designed with microcontrollers or complex programmable logic devices (CPLDs). However, increased complexity and more realtime data analysis have called for the development of digital signal processors (DSPs). The DSPs have very good programmability and can easily manage conditional code. Due to their ability to work with floating point arithmetics, they can handle complex mathematical functions well.
Alternatively, the applicationspecific integrated circuit (ASIC) may be used, where all the functions are designed into a fixed integrated circuit. The ASIC has to implement all functions in gates and very complex conditional programs may result in very poor gate utilization. Also, the ASIC is limited to fixed point arithmetic. As the gates can be programmed in parallel, the ASIC can operate simpler logic at a much faster rate than its DSP counterpart. However, once the ASIC is designed and manufactured, it cannot be modified for bugs or changed system characteristics, which makes it less useful in development projects.
The advent of the FPGA has resolved this issue and makes it superior to the ASIC for researchers and developers. Even though the FPGA requires much more area and power consumption and is about three times slower than its ASIC counterpart [5], its short time to market and fieldprogrammable ability make it a tempting solution.
The FPGA structure is based on a matrix of controllable logic blocks (CLBs). These consist of a lookup table (LUT), which can be configured either as a RAM/ROM or as logic functions, and a Dtype flipflop that can handle, for example, registers. The CLBs are interconnected by a programmable wire network, synchronized with a top level clock. Modern FPGAs can also have extra inbuilt features such as dedicated DSPblocks that can handle complex computations in one clock cycle. Also, external LUT blocks may be used as memory.
The use of FPGA technique within power electronics is mostly seen where rapid input/output (I/O) is requested. Reviews of control system implementation in FPGA is found in [6–8]. Grid impedance analysis using FPGA are done in [9]. An FPGAbased grid phase tracking method is described in [10], and pulsewidth modulation (PWM) implementations for inverters are found in [11, 12]. A combination of DSP and FPGA for SVMcontrol of a matrix converter is used in [13], and more FPGAbased SVPWM implementations can be found in [14, 15]. FPGAimplementations for fault detection in a VSI control is made in [16].
In this paper, the control system of a gridconnected CCVSI has been designed and implemented on an FPGA. The control system includes phase tracking of the grid voltage, inverter logic output control, active and reactive power flow control, highspeed burst logging, and fault detection. Hardware implementations are discussed as well as their limitations and the number of gates required for specific functions are summarized. The control system is implemented on the FPGAchip of a compactRIO module, and the VHDLcode is generated by LabView Gcode. The system allows for integration of a RTcontroller if heavier data analysis is required. The practical viability of the system is evaluated in an experimental setup with a gridconnected VSI. 30 kW at unity power factor is injected into the local electric grid, and the currentcontrol loops are evaluated by making step responses in the active power flow.
2. FPGA Programming
The initial step in FPGA design is to define the algorithms used. An algorithm can be characterized by its complexity and time constraints. The accuracy of I/Ovariables is set by their bit sizes.
Once this is done, the possibility of reusing modules in the system has to be explored. By smart time sharing, an algorithm may be put as a subroutine and routed to several different parts of the FPGA module. Finally, the same function may be expressed in different ways with the logic gates available. The most gateefficient algorithm should be used, based on the available gate resources on the FPGA. There are various ways of implementing the VHDLcode on the FPGA. Many compilers offer the programmer to write in a more userfriendly language, which seldom is as efficient as direct VHDLprogramming. The conversion into VHDL from another language will be a compromise between compilation time, space optimization, or clock cycle optimization. Below, a few key functions are summarized.
2.1. Integer Numbers
The fundamental building blocks of an FPGA are best utilized with integer maths operations. Floatingpoint (FP) operation is possible but provides poor utilization of the logic cells [17]. If decimal points are required, fixedpoint numbers (FXP) are used instead. A FXP is predefined by its bit length and the number of bits allocated for decimal accuracy and may be signed or unsigned. One drawback of FXP compared with FP is that they rapidly grow in size with the computations performed on them. Care must be taken to avoid saturation or overflow of a FXP. An evaluation of FXP precision is found in [18, 19].
2.2. Integer Multiplication
While adding and subtracting are rather straightforward operations with little space demand on the FPGA, multiplication is a big “gatehog” that should be avoided if possible. However, if the multiplication is fixed, this is not true if the multiplying factor is a multiple of 2. Multiplication with may easily be replaced with a decimal point shift times to the left or right on the FXP. This requires no resources, since it is only a matter of rerouting of the FXP between logic cells. If the multiplying factor cannot be approximated to a factor of 2, it may be simplified to a sum of fractions of 2 and then added. For example, the multiplier 1/3 may be approximated as which will give an error of about 0.4%. Depending on the accuracy required, the number of fractions may be varied. Figure 1 shows the implementation of this. The resource allocation for the proposed method compared to using a normal multiplication block is shown in Table 1 for implementations on a Xilinx5 chip. Here, the first method can save approximately 2% of the dedicated DSP blocks on the FPGA. Implementation of division should be converted into multiplication instead, as this will save lots of space.

2.3. Integrals
On the contrary to derivatives, the integral of a signal is very straightforward on the FPGA. The integral of may be approximated as a finite sum according to where is the sampling time and is assumed constant here. By using shift registers, the cumulative value of the signal is stored locally in the CLB and used directly for the next loop cycle as shown in Figure 2. The sampling time sets the accuracy of the integral and is also used as a scaling factor for the output.
2.4. Advanced Functions
More advanced calculations, for example, trigonometric, logarithmic, or squareroot functions, would require large amounts of resources if implemented as in a DSP counterpart. In the early age of FPGA, work was put into expressing these functions as combination of the simpler blocks [20]. As memory sizes grew, the use of lookup tables (LUTs) became a better option. Today, generic DSP blocks are often integrated on the FPGA semiconductor chip, and may perform these high throughput computations within one clock cycle. In Table 2, a resource comparison is done between a sine/cosine LUTblock and a trigonometric computational block producing the same output, implemented on the Xilinx5. The speed, resolution, and functionality of the two are equivalent, but it is clear how the LUT locks up one third of the total block RAM available, making it less attractive. However, the RAM space demand of the LUT will decrease proportionally with reduced output resolution.

3. Grid Phase Tracking
There are various known methods of tracking , the grid phase. Zerocrossing detection is a simple method to implement but is sensitive to noise and does not give any phase information between the zerocrossings. More advanced methods include the phaselocked loop (PLL), Kalman filters, or the discrete Fourier transform (DFT). A good comparison between these may be found in [21]. In this paper, grid phase tracking is performed using a threephase synchronous reference frame PLL loop, due to its robustness and relatively simple implementation. The PLL structure is shown in Figure 3.
The closedloop transfer function of the PLL can be written as [21] where and are the gains of the PIcontroller and is the sampling time of the PLL. If the sampling frequency is sufficiently high, the above expression can be simplified to
The sampling frequency is usually set to the switching frequency or half of it, depending on the control algorithm used. The design of the PLL is discussed in [22, 23] and is a compromise between speed and noise immunity. A discrete bitstream PLL implementation is discussed in [24].
4. Power Flow Control
Assuming a stiff grid, the active power and reactive power for a gridconnected VSI are governed by where is the grid voltage, the inverter voltage, the phase angle and the reactance between the VSI and the grid.
To simplify the currentcontrol feedback system, all phase currents are transformed into the frame by: where is the Clarke/Park transformation matrix [25]:
In this paper, the sinusoidal pulsewidth modulation (SPWM) will be used [26], where a control signal is compared with a carrier wave signal to generate the inverter output pulses. is generated by where and are currentcontrol feedback variables used to control the active and reactive power flows. The amplitude modulation index is and the load angle is . If , the inverter fundamental output phase voltage is derived as
5. Experimental Setup
The oneline diagram of the experimental setup is shown in Figure 4. The threephase inverter is made from 3 dualpackage 400GB126D IGBT modules with 2SC0108T2Ax17 driver boards mounted above, as shown in Figure 5(a). These have inbuilt shortcircuit protections set to trigger 2.5 μs after fault detection. The inverter is directly connected to a threephase 345 V/1 kV YYconnected transformer. The transformer ratings are given in Table 3.

(a)
(b)
An LCLfilter is placed on the secondary side of the transformer. The primary and secondary filter inductors are both designated the value of 1.5 mH. These are manufactured on two threephase cores and there is an unbalance between the phases of 10%. The shunt capacitors are connected in star configuration with 20 μF per phase. The grid main voltage at the point of common coupling (PCC) is 400 V at 50 Hz.
A compactRIO NI9014 module with integrated RTcontroller and FPGA chip from the National Instruments was used, as shown in Figure 5(b). The FPGA chip is of model Xilinx5 [27] with an internal clock frequency of 40 MHz. The RTcontroller is of the model NI9022. Two of the four available I/Oslots in the chassis are used. In the first, an NI9205 analogue differential input module is put for data sampling. It has a total of 16 available channels when set in differential mode, with an analoguetodigital conversion (ADC) speed of 250 kS/s for a singleended input, and 16 bit resolution. A differential input requires three times the sampling time. In the given control strategy, seven measurements have to be made: 3 grid voltages, 3 grid currents, and 1 DC voltage measurement. (To slim the system further, only two voltage and current measurements may be used for the grid, if the system neutral is floating.) The hardwired ADC MUX will share these equally, allowing the sampling frequency to reach 11.9 kHz. The second I/Oslot in the chassis is used for the inverter control signal output. Here, an NI9401 module is utilized, with 8 digital outputs, each with a delay time of 8 μs. For the threephase inverter, only six of the outputs are required.
6. FPGA implementations
The control system of Figure 4 was implemented using Labview Gcode. This is compiled into VHDLcode before programmed onto the FPGA chip. The advantage of using Labview is a relatively userfriendly interface, with the drawback of a not completely optimized VHDL design and some limitations in the code writing.
A general overview of the various control loops is found in Figure 6. All the necessary parts of the system are implemented in the FPGA. As can be seen, there is also provision to connect a RTcontroller and a PC. These are not crucial for the control system but provide auxiliary functions. The RTcontroller can be used for harmonic analysis of the grid currents, fault handling, and transfer of data from the FPGA burst log. The burst log is triggered at any fault detection like an overcurrent. The PC works as a remote interface and longterm data.
The gate utilization of all the functions implemented above is summarized in Table 4. This is not claimed to be completely optimized. Also, some auxiliary functions for initializing the system and general protections are excluded, as they are not the scope of this paper. The dominant delay time of the control system is the input sampling time of the ADCs, requiring 12 μs per sample. The data processing and internal logic have time delays in the order of ticks, which become negligible in comparison. To improve the system dynamics further, the ADCs must become faster.

Below, the major functions are described.
6.1.  Transformation
The transform is used in both the PLL and the currentcontrol loop. It is implemented as a subroutine and used for the two instances. As can be seen in Figure 6, the subroutine is implemented in series for the two computations, making it possible to reuse more efficiently. In the calculation of the SPWM control signals, , the transform is used instead, and this has to be coded separately. However, the terms and are still the same and may be called by local variables for a more efficient gate utilization. If we assume a balanced, steady state threephase system, the 0component may be omitted, and so the Clarke/Park transform is reduced to
Since the FPGA used has generic DSPblocks, some of these are used for generation of sine and cosine waveforms as discussed in Section 2.4. For any trigonometric phase input, a 16bit output is generated within one clock cycle. However, trigonometric functions are still rather space demanding, and the matrix transformation in (10) requires six of these. Alternatively, can be calculated by which only requires two trigonometric functions but has two extra multiplication functions instead. The two implementations of the transformation are illustrated graphically in Figures 7 and 8. A comparison of the gate utilization for the two types is found in Table 5. In this case, there is no difference between the two, but it illustrates how the same function can be implemented in different ways. If the trigonometric functions are more gate demanding, type 1 is more efficient, whereas if the multiplication blocks are more gate demanding, type 2 should be selected. In the experimental setup, type 1 has been implemented.

6.2. PLL
The major delay of the PLL loop is the grid voltage ADC delay times. This sets the loop frequency at 11.9 kHz, which is sufficient for the reduction of (3) to (4). The integral of the frequency to get the phase is done by the procedure explained in Section 2.3. The PIcontroller can be implemented by either using shift registers or using the generic DSPblocks. Here, the latter is chosen, as it has slightly better dynamics at the expense of more gates required. The variables and are fed into local variables that may be used in parallel loops on the FPGA. Local variables are designated double frames in Figure 6.
6.3. SPWM and Current Control
Calculation of the bipolar SPWM control signals for all three phases is done with the inverse Clarke/Park transformation, reusing the trigonometric results from the PLL by the local variables mentioned above. The inverter digital outputs are generated by comparison of with a carrier waveform like a sawtooth wave or a triangular wave. The harmonic content of does not differ much between the two [28]. Here, the sawtooth wave is selected due to its easiness to implement. To implement the sawtooth wave, a simple counter with 2N steps is used, starting at − and going up to . If the SPWM loop time shown in Figure 6 takes to run once, the switching frequency of the sawtooth wave can be calculated as where is the clock frequency of the FPGA; here it is 40 MHz. If the SPWMloop is put in series with the PLL, the run time becomes μs. If the required is 3.5 kHz, the resolution of the carrier wave becomes limited to 4 steps, making the output useless. Since will not change significantly between sampling times, it is valid to put the SPWM loop as a parallel process on the FPGA. Now the SPWM loop time is only 8 ticks, and by setting, for example, steps, we obtain a switching frequency of = 4.88 kHz. This gives a good compromise between switching frequency and carrier wave resolution. The switching frequency may be altered either by changing or introducing a delay time to prolong .
The control variables and are derived by comparing the measured with the set and applying two PIcontrol blocks on the result. is always set to zero to get unity power factor into the grid. is derived based on the difference of the measured and the set . To reduce the effects of harmonics and noise on the current signals, a moving average filter is applied on . This is easily implemented by calculating the mean of the last 100 measured values, stored in shift registers.
7. Results and Discussion
Initially, the PLL was tested by simulating a threephase grid voltage internally on the FPGA, using LUTs. In Figure 9(a), the grid phase for a distortionfree 50 Hz grid voltage is tracked by the PLL with perfect results. In Figure 9(b), 5% of the 3rd, 5th, and 7th harmonics are added to the grid voltage. The phase tracking is still stable and does not completely follow the grid phase harmonic derivatives since these will be partially filtered out by the PLL transfer function.
(a)
(b)
In Figure 10(a), the timedomain zerocrossings of the grid voltage and the PLL signal are compared. The PLL is updated with the analogue input sampling time of 84 μs and is set constant in between. Since the grid voltage does not change significantly between samples, the discrete PLL is a good representation of the grid voltage. In Figure 10(b), the noise immunity of the PLL is evaluated. Here, 20% Gaussian noise is added to the grid voltage, and as can be seen this is effectively filtered out by the PLL, since the integrals act as a lowpass filter.
(a)
(b)
Figure 11 shows the three phase currents at 30 kW active power injection into the grid. The reactive power flow is set to zero. The system is stable, but there is a minor unbalance between the phase currents, due to an unbalance in the harmonic LCLfilter. This can be mitigated by either compensation of the SPWM control signals, or the control system can be extended to three individual currentcontrol loops, one per phase. However, this mitigation will not be linear due to the power transformer that will try to cancel any voltage unbalances by its internal flux. For a more stable currentcontrol loop, symmetrical filtering may be applied to the measured currents.
With intermittent renewable energy sources, there may be a swift change in power input to the grid, unless there is some intermediate energy storage. Thus, the currentcontrol system has to manage step responses in active power while still keeping reactive power flows at the desired level. In Figure 12, a stepup response is made from 1 kW to 21 kW while keeping the desired reactive power flow zero, and in Figure 13 the corresponding stepdown response is performed. Since the grid voltage is stable, is directly proportional to the active power and proportional to the reactive power.
Due to the distortion in the grid voltage, the injected current will carry lower order harmonics, which cannot be removed by the lowpass LCLfilter. These are clearly present in the ripple of of Figures 12 and 13. The presence of these harmonics makes it harder to tune the sensitivity of the currentcontrol feedback loops, and there are two ways of resolving this. Either, the 50 Hz fundamental frequency of the currents is filtered by a highorder bandpass filter. This is preferably implemented as an analogue filter, as its FPGAimplemented counterpart, though possible, will require a large number of gates. The other way is by filtering the currents. In frame, the DCcomponent corresponds to the fundamental frequency, and a simple moving average filter will do the trick. However, this will reduce the speed of the currentcontrol. The method chosen depends on the required sensitivity of the currentcontrol loop. In this paper, a smoothing movingaverage filter has been applied on the FPGA. The moving average values of the currents can be seen as dotted lines in the figures and are used as inputs for the PIcontrollers. The resultant current response takes a few cycles to settle at the new power level but is sufficiently good for these kind of applications.
It is also worth pointing out how the sudden step change in active power results in a fluctuation of reactive power, which reflects the coupling of the two in (5). A stepup change in results in a drop of reactive power . This is counteracted by the feedback control loop by increasing till again has settled at zero. The increase in will give a further increase in active power, and finally the system settles at a new steadystate point. The inverse phenomena occur for the stepdown case. For step changes within these ranges, and can confidently be treated by separate control loops with relatively stable outputs. The response time can be decreased further by tuning the PIcoefficients more aggressively. If the oscillations between and become an issue, feedforward crosscoupling terms may be introduced to make the control loop more dynamic.
8. Conclusions
In this paper, the control system for a gridconnected currentcontrol VSI has been designed and implemented on an FPGA, which differs from the more conventional microprocessorbased implementations. The system has proven viable for a gridconnected VSI supplying the local grid with 30 kW and full reactive power control. The development of FPGA technology, especially the generic DSPblocks, makes this a competitive control hardware and is very suitable for development projects. Also, a complementary system may be used if heavier computations or data logging is required. In the article, a RTcontroller is used for, for example, harmonic analysis, burst log, and fault detection.
A PLL is implemented and shows steady phase tracking of the grid voltage. Grid voltages have been simulated with added harmonic contents and noise, still maintaining a stable phase tracking in the PLL.
There is a minor unbalance between the phase currents, due to an unbalance in the LCLfilter. This can be relieved by individual phase control of the inverter. Step responses have been performed in active power, while maintaining the reactive power at zero. Due to the lowerorder harmonic content of the grid currents, a moving average filter is added to get smoother control variables. This results in a stable but slightly slower step response. In the power range evaluated,  and control can be treated with uncoupled current control loops, still maintaining stable step responses. To reduce the oscillations further, feedforward crosscoupling terms have to be added between and .
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Copyright
Copyright © 2013 Rickard Ekström and Mats Leijon. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.