Fault-Tolerant Control Strategy for Neutral-Point-Clamped Three-Level Inverter

Shen, Yanxia; Miao, Beibei; Wu, Dinghui; Ali Ibrahim, Kader

doi:https://doi.org/10.1155/2018/5126404

Journal of Control Science and Engineering

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Abstract Introduction Conclusion Conflicts of Interest Acknowledgments References Copyright Related Articles

Research Article | Open Access

Volume 2018 | Article ID 5126404 | https://doi.org/10.1155/2018/5126404

Fault-Tolerant Control Strategy for Neutral-Point-Clamped Three-Level Inverter

Yanxia Shen,¹Beibei Miao,¹Dinghui Wu,¹and Kader Ali Ibrahim¹

Academic Editor: Ahmed Rhif

Received15 Sept 2017

Accepted31 Dec 2017

Published01 Feb 2018

Abstract

A fault-tolerant control technique is discussed for the Neutral-Point-Clamped (NPC) three-level inverter, which ensures that the NPC inverter operates normally even under device failures. A two-level leg is added to the NPC inverter; when the device open circuit fault occurs, the load of this faulty phase is connected to the neutral point of this two-level leg through the bidirectional thyristors. An improved Space Vector Pulse Width Modulation (SVPWM) strategy called “addition and subtraction substitution SVPWM” is proposed to effectively suppress fluctuation in capacitor neutral-point voltages by readjusting the sequence and action time of voltage vectors. The fault-tolerant topology in this paper has the advantages of fewer switching devices and lower circuit costs. Experimental results show that the proposed fault-tolerant system can operate in balance of capacitor neutral-point voltages at full output power and the reliability of the inverter is greatly enhanced.

1. Introduction

Compared with the conventional two-level inverters, multilevel inverters have the advantages of lower voltage stress, better waveform spectrum, less voltage change rate, and waveform distortion [1–3]. Therefore, it is widely used in various electric power conversion and power transmission applications, such as inverter system, low-voltage motor drives, and wind power generation [4–6]. However, there are many switching devices in multilevel inverters, and the control of these switches becomes more complex, which leads to a significant increase in failure rate. Then the reliability of the circuit is greatly deteriorated. If the open fault is not dealt with in time, the voltage stress of certain switch will increase owing to the fluctuation of capacitor neutral-point voltages. What is worse, the entire circuit operates abnormally, causing serious accidents or incalculable economic losses [7–9]. In some applications, higher reliability of the circuit is required that it is even expected that the circuit should keep working for a period under the device failures. So, in recent years, the research of fault-tolerant control for multilevel inverters has attracted wide attention from scholars [10–12].

For three-level inverters, there are a variety of fault-tolerant control methods. The fault-tolerant control of the Active Neutral-Point-Clamped (ANPC) inverter using the redundant switching states has been proposed in [13]. The inverter can operate in balance of capacitor neutral-point voltages with symmetrical three-phase output after the proposed fault-tolerant control method is applied. However, the amplitude of output voltage and current are greatly decreased. A load-type fault-tolerant solution of the ANPC inverter has been proposed in [14, 15]. The basic idea of this method is to keep the faulty leg at O level, which is achieved by connecting the faulty leg to the neutral point of the DC-link capacitor. Similarly, the inverter can only operate at reduced rated power. The fault-tolerant of half-bridge switches and neutral-point switches in T-type inverter has been proposed in [16, 17]. The redundant switching states are used to synthesize the reference vector of the rotational voltage in SVPWM algorithm, which enables the inverter to operate normally in the fault condition. However, for the open fault of half-bridge switches, the DC-link voltage utilization ratio is half of this inverter. The fault-tolerant control of the T-type inverter using the additional leg has been proposed in [18]. The one-phase bridge of the T-type inverter is used as the additional leg. Once a fault is detected, the faulty phase is connected to the additional leg by the corresponding bidirectional thyristors. The inverter can output the full-rated power in any fault condition, with higher manufacturing costs and larger size and weight. The eight-switch three-phase inverters (ESTPIs) reconfigured topologies for the NPC inverter have been proposed in [19]. When the device open circuit fault occurs, the corresponding bidirectional thyristors of the faulty leg is triggered, and the faulty leg is connected to the neutral point of the DC-link capacitor. However, the inverter can only operate at half output power; also the amplitude of the output voltage is decreased by half. The fault-tolerant control of the NPC inverter using the asymmetric leg has been proposed in [20]. The faulty leg is isolated by the bidirectional thyristors under device failures, and an asymmetric two-level leg is added to the inverter. To eliminate the low-order harmonic component of the output phase voltages, the bipolar Sinusoidal Pulse Width Modulation (SPWM) method is used to control the asymmetric leg. The inverter can operate in balance of three phases’ output without reducing the output power of the original circuit. A software redundancy fault-tolerant control algorithm of the NPC inverter has been proposed in [21]. This method is implemented by using the redundant voltage vectors, with some limitations that apply only to open circuit fault and short circuit fault of outer switches.

When the open circuit fault of inner switches occurs in the NPC three-level inverter, some voltage vectors are lost, and the synthesis of the possible voltage vectors for reference voltage cannot be implemented. Consequently, the reconfiguration of the circuit is required for fault-tolerant control. In order to ensure the NPC inverter can output the full-rated power under device failures, a two-level leg serves as the additional leg for the faulty phase in this paper. When the open circuit fault occurs in the NPC inverter, the faulty leg is connected to the additional leg through the bidirectional thyristors. Both the switching states P and N, generated by modifying the SVPWM algorithm, are employed to control the additional leg. In addition, in order to accurately suppress the fluctuation of the capacitor neutral-point voltages, an improved SVPWM strategy called “addition and subtraction substitution SVPWM” is proposed to readjust the sequence and action time of voltage vectors in SVPWM algorithm.

2. Description of NPC Inverter

Figure 1 shows the main circuit of NPC three-level inverter. There are three switching states for each leg [22], namely, P, O, and N. For instance, the relation between switching states and switching sequence of phase A is listed in Table 1.

In Table 1, “1” indicates that the power device is turned on and “0” indicates turn-off. The symbol “+” represents the current flows from the power supply to the load; on the contrary, the symbol “−” represents the current flows from the load to the power supply.

It can be known from Figure 2 that the NPC inverter has 27 combinations of switching states that correspond to 27 space voltage vectors, divided into four classes according to their magnitudes, namely, zero-, small-, medium-, and large-voltage vectors [23, 24].

3. Effect of the Switching States on Neutral-Point Voltages

When the open circuit fault occurs in NPC three-level inverter, the absence of the switching states leads to the change in the current flow paths. Consequently, an undesirable bridge arm phase voltage is generated, which can bring out the distortion of the load phase current, resulting in the fluctuation of the capacitor neutral-point voltages. The analysis is illustrated with QA1 and QA2 single-switch fault of phase A. The direction of the current flows from the power supply to the load is defined as the positive direction .

(1) QA1 Fault. The current can only flow through the switch QA2 and the diode D5 to the load under the switch QA1 fault, while the inverter operates in the P state and the current . The load is connected to the neutral point of DC side and the inverter operates in the O state, as shown in Figure 3(a). The solid line represents that the inverter operates normally, whereas the dotted line denotes the inverter under the QA1 fault condition. The bridge arm phase voltage varies from to zero, which causes the distortion of load phase current. Under these circumstances, all voltage vectors that start with “P” are undesirable, including small-voltage vectors [PPO], [POO], and [POP]; medium-voltage vectors [PON] and [PNO]; and large-voltage vectors [PNN], [PPN], and [PNP], as shown in Figure 4(a). These impossible voltage vectors are replaced by the voltage vectors enclosed with brackets that start with “O”; conversely, the voltage vectors that start with “O” or “N” state in phase A are desirable, because the QA1 fault has no effect on them. That is, the number of the current branches flowing to load from the neutral point of DC side is more than that in the normal state. Therefore, the upper capacitor voltage is greater than the lower capacitor voltage .

(a)

(b)

(a)

(b)

(2) QA2 Fault. As illustrated in Figure 3(a), one condition is that the QA2 fault occurs in the case that the inverter operates in the P state and the current , the current flows through the diodes D3 and D4 to the load, and the inverter operates in the N state. This condition brings out the change in the magnitude of bridge arm phase voltage and current. The other one is that the inverter operates in the O state and the current . In the same way, the current flows through the diodes D3 and D4 to load, and the switching state is N, as shown in Figure 3(b). The solid line means the inverter in the normal state and the dotted line indicates the inverter under the QA2 fault condition. Thus, it can be observed from Figure 4(b) that all voltage vectors beginning with “P” and “O” are crossed out and these voltage vectors are replaced by the voltage vectors beginning with “N”; the number of the current branches flowing to load from the neutral point of DC side is less than that in the normal state. Similarly, it can be derived that is greater than .

In summary, the device open circuit fault can cause unbalance of the capacitor neutral-point voltages in the NPC inverter.

4. Fault-Tolerant Topology and Working Principle

As shown in Figure 4, when the QA1 open circuit fault occurs, the equivalent stator flux circle can still be synthesized by adjusting the sequence of the available voltage vectors based on vector superposition theorem, but the voltage utilization ratio is half. In contrast, the inverter has no fault tolerance ability in case of the QA2 fault because there is no redundant voltage vectors to synthesize the stator flux circle in the area . Therefore, in order to enable the NPC inverter to operate at full output power under the device failures, a two-level leg is added to the main circuit of the NPC three-level inverter, which consists of two switches Q1 and Q2 and corresponding antiparallel diodes D19 and D20. In addition, six bidirectional thyristors Trx1 and Trx2 (, , and ) are used to constitute the fault-tolerant topology of the NPC inverter, as shown in Figure 5.

When the NPC inverter operates normally, Trx1 (, , and ) are connected and Trx2 (, , and ) are disconnected. If the open fault of phase A occurs, the faulty phase is isolated by Tra1, and the midpoint O′ of this two-level leg is connected to load of the faulty phase through Tra2. Both the switching states P and N, generated by modifying the SVPWM algorithm, are aimed at controlling the two switches Q1 and Q2 of this two-level leg. Obviously, the O state is not available. It is essential to readjust the sequence and action time of voltage vectors. In general, the proposed reconfiguration topology can maintain the neutral-point voltages balance and operate at full output power under any fault condition.

5. SVPWM Strategy of Addition and Subtraction Substitution

After the fault reconstruction topology is adopted, different voltage vector distribution can be obtained, as illustrated in Figure 6.

The equivalent stator flux circle can still be synthesized by adjusting the sequence of the available voltage vectors, and the inverter can output the full-rated power. An improved SVPWM strategy called “addition and subtraction substitution SVPWM” is proposed to effectively suppress the fluctuation of the capacitor neutral-point voltages. The fault-tolerant control of NPC inverters is carried out by adjusting the sequence and operation time of voltage vectors. The research is conducted only taking phase-A fault as an example.

If the phase-A fault occurs, the faulty phase A is replaced with a two-level leg, which is controlled by the switching states P and N. Therefore, the switching states that start with “O” are prohibited, as shown in Figure 6, and these undesirable voltage vectors should be replaced by other voltage vectors of the same size. Namely, N-type voltage vectors ([OON], [ONN], and [ONO]) in the regions I, II-1, II-3, II-5, and VI are replaced, respectively, with P-type voltage vectors ([PPO], [POO], and [POP]). For the purpose of restraining the fluctuation of the capacitor neutral-point voltages effectively, P-type voltage vectors ([OPO], [OPP], and [OOP]) in the opposite regions IV, V-1, V-3, V-5, and III should be replaced, respectively, with N-type voltage vectors ([NON], [NOO], and [NNO]). However, there are no redundant voltage vectors in the medium-voltage vectors ([OPN] and [ONP]) in regions II and V. In this paper, the medium-voltage vectors are replaced by the small-voltage vectors adjacent to them. Table 2 presents the substitution law of voltage vectors in each region.

“Addition and subtraction substitution SVPWM” is simply defined by adding or subtracting a minimum action time () to the three-phase action times (, , and ) to realize the substitution of voltage vectors in the SVPWM algorithm. The sequence and action time of voltage vectors are adjusted by replacing the undesirable voltage vectors with the remaining voltage vectors of the same size, where represents the minimum value among , , and . In this method, the N-type voltage vectors can be substitute for the P-type voltage vectors after is added to , , and . In contrast, the P-type voltage vectors take the place of the N-type voltage vectors by subtracting to , , and . The process will be explained in two regions I-1 and III-2.

The sequence and action time of voltage vectors in region I-1 in the normal state are shown in Figure 7(a). The undesirable N-type voltage vectors [ONN] should be replaced by the P-type voltage vectors [POO], and this process is achieved by subtracting in three-phase action times (, , and ), as shown in Figure 7(b), where is . Similarly, the impossible voltage vectors [OON] and [OOO] should be changed to [PPO] and [PPP]. Finally, according to the principle that the switching states can only be changed once or unchanged, the redefined sequence and action time of voltage vectors should be rearranged, as shown in Figure 7(c).

(a)

(b)

(c)

The sequence and action time of voltage vectors in region III-2 in the normal state is shown in Figure 8(a). In order to replace the impossible P-type voltage vectors [OPO] with N-type voltage vectors [NON], is added in three-phase action times (, , and ), where is . The redefined sequence and action time of voltage vectors can be obtained as given in Figure 8(b). Therefore, the redefined sequence and action time of voltage vectors in each region listed in Table 3 can be summed up.

(a)

(b)

, , and represent the action time of voltage vectors corresponding to the different switching sequence.

6. Experiment Verification

In order to validate the improved SVPWM strategy proposed previously, a laboratory prototype of the NPC three-level inverter with fault-tolerant capability is built based on the dSPACE DS1007 platform, as shown in Figure 9. The main experimental parameters are listed in Table 4. Figure 9 shows the overall structure of the experimental platform, including NPC inverter, three-phase load, DS1007, and PC. The main boards used in the experiment are DS5202 and ACMC (AC Motor Control). DS5202 provides 8 channels with maximum sampling frequency of 10 MHz, and EV1048 not only can be used for AD sampling but also generate PWM signal to drive the inverter circuit. In the experiment, the QA1 open fault is set up and fault-tolerant control is carried out.

Figure 10 shows the different experimental waveforms of the output voltages, current, and capacitor neutral-point voltages without and with fault-tolerant control in sequence. The waveforms of phase-A bridge arm phase voltage and line-to-line voltage are given in Figure 10(a), respectively. It can be observed from Figure 10(a) that the phase voltage exhibits three levels and the line-to-line voltage shows five levels under the normal condition. When the fault occurs, the amplitude of the phase voltage in positive half period is decreased from to zero, and a zero level appeared for a long time. Similarly, the amplitude of line-to-line voltage in positive half period is lower than that of the normal condition. The voltage waveforms are the same as that under the normal condition when the proposed method is adopted for fault-tolerant control; namely, is three-level waveform with constant output amplitude and is five-level waveform with constant output amplitude.

(a)

(b)

(c)

(d)

Figure 10(b) shows the waveforms of current in phase-A without and with fault-tolerant control, respectively. It can be seen from Figure 10(b) that the current is sinusoidal before the fault occurs, but when the fault occurs, the amplitude of the load phase current in positive half period is approximately reduced to half of the normal condition, and the waveform is obviously distorted. The load phase current is still sinusoidal with constant amplitude after the proposed fault-tolerant method is applied, and the inverter can operate normally.

Figures 10(c) and 10(d) show the capacitor neutral-point voltages without and with fault-tolerant control, respectively. As shown in Figure 10(c), when the fault occurs, the neutral-point voltage of the capacitor fluctuates obviously, and . The fluctuation of the neutral-point voltage of the capacitor is well suppressed by the fault-tolerant control, as shown in Figure 10(d). Obviously, the correctness of the fault-tolerant strategy is proved by experiments.

7. Conclusion

In order to enable the NPC inverter to operate at full output power under the device failures, a two-level leg is taken as the additional leg of the faulty phase in this paper, which is controlled with the two switching states P and N. In addition, an improved SVPWM strategy called “addition and subtraction substitution SVPWM” is proposed to readjust the sequence and action time of voltage vectors in SVPWM algorithm. The main advantages of the proposed fault-tolerant SVPWM strategy include the following:

(1) The proposed fault-tolerant topology has fewer switching devices and lower costs.

(2) The inverter is operated continuously without reduced output power by the proposed method. Therefore, the proposed fault-tolerant SVPWM strategy can be applied for all kinds of applications.

(3) The distortion of capacitor neutral-point voltages is eliminated well after the proposed fault-tolerant method is applied.

(4) The two switches Q1 and Q2 of this two-level leg should withstand the entire input DC voltage after fault-tolerant control. Therefore, the proposed method is more suitable for the NPC inverter with medium- or low-voltage power supply.

The effectiveness and fault-tolerant operation of the proposed SVPWM strategy are demonstrated by both simulation and experimental results under various types of faults.

Conflicts of Interest

The authors declare that they have no conflicts of interest regarding the publication of this paper.

Acknowledgments

This work is supported in part by the National Natural Science Foundation of China (61573167 and 61572237). The authors appreciate the support of the Priority Academic Program Development of Jiangsu Higher Education Institutions as well as The Research Innovation Program for College Graduates of Jiangsu Province, SJLX16_0107.

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Copyright © 2018 Yanxia Shen et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

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