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Journal of Engineering
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2013
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Article
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Tab 1
Research Article
Static Switching Dynamic Buffer Circuit
Table 1
Comparison of power saving with different logic functions in 0.18
μ
m (VDD = 1.8 V, clock frequency = 200 MHz, input frequency = 50 MHz, and load capacitance = 100 fF).
Logic function
Standard footless circuit (
W)
The proposed circuit (
W)
Power saving by the proposed circuit
A
394.95
68.602
82.63%
A · B
263.86
70.249
73.37%
A + B
391.33
68.706
82.44%
A · B · C
200.82
72.417
63.93%
A + B + C
400.14
69.257
82.69%
A · B · C · D
177.74
75.064
57.76%
A + B + C + D
403.58
69.587
82.75%