Journal of Engineering / 2013 / Article / Tab 1

Research Article

Static Switching Dynamic Buffer Circuit

Table 1

Comparison of power saving with different logic functions in 0.18 μm (VDD = 1.8 V, clock frequency = 200 MHz, input frequency = 50 MHz, and load capacitance = 100 fF).

Logic functionStandard footless circuit ( W)The proposed circuit ( W)Power saving by the proposed circuit

A394.9568.60282.63%
A · B263.8670.24973.37%
A + B391.3368.70682.44%
A · B · C200.8272.41763.93%
A + B + C400.1469.25782.69%
A · B · C · D177.7475.06457.76%
A + B + C + D403.5869.58782.75%