Static Switching Dynamic Buffer Circuit

Table 1

Comparison of power saving with different logic functions in 0.18 μm (VDD = 1.8 V, clock frequency = 200 MHz, input frequency = 50 MHz, and load capacitance = 100 fF).

Logic function	Standard footless circuit (𝜇W)	The proposed circuit (𝜇W)	Power saving by the proposed circuit
A	394.95	68.602	82.63%
A · B	263.86	70.249	73.37%
A + B	391.33	68.706	82.44%
A · B · C	200.82	72.417	63.93%
A + B + C	400.14	69.257	82.69%
A · B · C · D	177.74	75.064	57.76%
A + B + C + D	403.58	69.587	82.75%