Research Article
A Very Compact AES-SPIHT Selective Encryption Computer Architecture Design with Improved S-Box
Table 10
Comparison with other Rouvroy et al.’s designs in terms of code execution and speed.
| | | Rouvroy’s AES | Rouvroy’s AES | Rouvroy’s DES | Rouvroy’s 3DES | CISA AES |
| | Device | XC3S50-4 | XC2S40-6 | XC2S40-6 | XC2S40-6 | XCS1500L-4 | | Slices | 163 | 146 | 189 | 227 | 110 | | Throughput (Mbps) | 208 | 358 | 974 | 326 | 0.08 | | Block RAMs | 3 | 3 | 0 | 0 | 3 | | Throughput/area (Mbps/slices) | 1.26 | 2.45 | 5.15 | 1.44 | 0.728 kbps |
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