Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Figure 4

Proposed H-DyCML gates: (a) 2-input XOR gate; (b) 3-input XOR gate with two levels of source-coupled transistor pair in the PDN; (c) 3-input XOR gate with single level of source-coupled transistor pair in the PDN.

(a)

(b)

(c)