Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Table 1

Performance comparison of the existing DyCML and the proposed H-DyCML AND gate.

Parameter	Style
	DyCML	H-DyCML (Technique 1)	H-DyCML (Technique 2)		H-DyCML (Technique 3)
			PMOS	NMOS
Technology node 180 nm
Delay (ps)	192.31	176.01	167.92	162.13	180.54
Power (µW)	20.31	15.57	15.58	15.02	15.58
PDP (fJ)	3.90	2.69	2.61	2.43	2.81
Technology node 90 nm
Delay (ps)	180	156	129	164	168
Power (µW)	14.2	13.36	13.1	13.9	13.4
PDP (fJ)	2.55	2.08	1.68	2.27	2.25