Research Article
Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style
Table 2
Performance comparison of the existing DyCML and the proposed H-DyCML OR gate.
| Parameter | Style | DyCML | H-DyCML (Technique 1) |
H-DyCML (Technique 2) | H-DyCML (Technique 3) | PMOS | NMOS |
| Technology node 180 nm |
| Delay (ps) | 236.24 | 172.28 | 162.12 | 219.03 | 170.25 | Power (µW) | 32.11 | 13.762 | 13.83 | 13.88 | 13.94 | PDP (fJ) | 7.58 | 2.37 | 2.24 | 3.04 | 2.37 |
| Technology node 90 nm |
| Delay (ps) | 180 | 156 | 129 | 164 | 168 | Power (µW) | 14.2 | 13.36 | 13.1 | 13.9 | 13.4 | PDP (fJ) | 2.55 | 2.08 | 1.68 | 2.27 | 2.25 |
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