Research Article

Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Table 2

Performance comparison of the existing DyCML and the proposed H-DyCML OR gate.

ParameterStyle
DyCMLH-DyCML (Technique 1) H-DyCML (Technique 2)H-DyCML (Technique 3)
PMOSNMOS

Technology node 180 nm

Delay (ps)236.24172.28162.12219.03170.25
Power (µW)32.1113.76213.8313.8813.94
PDP (fJ)7.582.372.243.042.37

Technology node 90 nm

Delay (ps)180156129164168
Power (µW)14.213.3613.113.913.4
PDP (fJ)2.552.081.682.272.25