Hybrid Dynamic MCML Style: A High Speed Dynamic MCML Style

Table 4

Performance comparison of the existing DyCML and the proposed H-DyCML 3-input XOR gate with two levels of source-coupled transistors in the PDN.

Parameter	Style
	DyCML	H-DyCML (Technique 1)	H-DyCML (Technique 2)		H-DyCML (Technique 3)
			PMOS	NMOS
Technology node 180 nm
Delay (ps)	326.39	211.02	180.00	191.31	199.05
Power (µW)	26.54	14.84	14.84	13.23	12.32
PDP (fJ)	8.66	7.35	5.56	5.69	6.37
Technology node 90 nm
Delay (ps)	226	175	163	169	190
Power (µW)	23	16.2	16.8	18.4	16.7
PDP (fJ)	5.2	2.83	2.73	3.1	3.17