Orthogonal frequency division multiplexing (OFDM) is a powerful modulation choice for wideband wireless communication systems. However, its high peak-to-average power ratio greatly limits the high power amplifier (HPA) power efficiency. Here, we present the design of an adaptive predistorter to compensate the distortion caused by the HPA. Specifically, we deal with the implementation issue of the proposed predistorter in Lee and de Figueiredo's work (2006). The performance improvement by predistorter is verified by both floating-point simulation and fixed-point simulation, where the latter includes the distortion effects from the hardware. The bit widths for OFDM signals, ADC, and DAC are evaluated, and the bit width of 10 is shown to be sufficient for the hardware design.

1. Introduction

Othogonal frequency division multiplexing (OFDM) has attracted a lot of attention from the modern wireless communication community, because of its several desirable features for high-speed data transmission. In OFDM, a broadband signal is broken down into multiple narrowband subcarriers and implemented efficiently by using the IFFT algorithm [1]. OFDM advantages include: lower intersymbol interference, efficient use of frequency/spectrum through the use of different modulation/coding across subcarriers, and superior narrowband interference suppression capabilities. However, we need to consider the practical hardware limitations of low-cost RF and mixed signal devices when designing OFDM systems for broadband wireless data transmission. One of them is the high power amplifier (HPA) linearity and dynamic range, since OFDM signals have higher peak to average power ratios (PAPRs) than other high-performance modulations, and thus extra care is required. One of the most promising approaches to the mitigation of the PAPR problem is to use a predistorter applied to the OFDM signal prior to its entry into HPA. Its purpose is to compensate the nonlinearity of the HPA and improve the system performance. Many researchers have been investigating OFDM predistorter schemes [2ā€“5]. However, all of these techniques are based on a general approximation form for the nonlinear system, rather than exploiting specific forms gleaned from physical device considerations. Due to this reason, we proposed a closed-form predistorter represented by a few parameters [6].

In this paper, we will apply Rapp's SSPA model [7] for HPA devices and show the implementation plan of the predistorter which was introduced in [6]. Furthermore, this paper also provides the design of a tracking algorithm for the case in which the practical HPA is unknown and varying. Finally, the simulation results are presented to investigate the performance improvement from predistorter, and study the distortion effects caused by saturation, overflow, and quantization with different number of bit widths, since the bit width of OFDM baseband (OFDM BB) and DAC/ADC is limited by cost and design constraints in real systems.

2. System Description

As shown in the block diagram of Figure 1, the proposed OFDM predistorter is placed after the OFDM baseband (BB) block to compensate for the degradation function in HPA.

In Figure 1, š‘Ÿ, š‘ž, and š‘¢ are amplitudes of output of the BB, predistorter, and HPA block, respectively. From the normalized Rapp's SSPA model [7], we have š‘¢[š‘Ÿ]=š‘Ÿ(1+(š‘Ÿ/š“0)2š‘)1/2š‘,(1) where š‘¢ is the HPA output amplitude, š“0>0 is the maximum output amplitude from HPA, and š‘>0 is the parameter which controls the smoothness of the transition from the linear to the saturating region. Please note that the phase distortion for HPA is very small and hence can be neglected [7], and thus, the predistorter mainly focuses on amplitude compensation. In order to compensate the nonlinearity of the HPA, using the predistorter, the HPA output š‘¢ is targeted to be linear to š‘Ÿ. Thus, š‘ž(š‘Ÿ)(1+(š‘ž(š‘Ÿ)/š“0)2š‘)1/2š‘=š‘Ÿ.(2) Thus, we can derive the following equation [6]: š‘žš‘Ÿ(š‘Ÿ)=(1āˆ’(š‘Ÿ/š“0)2š‘)1/2š‘,š‘Ÿ<š“0.(3)

When š‘Ÿā‰„š“0, (3) has no solution, and š‘ž has to be clipped which will be explained in the following section. Figure 2 shows a compensation example of the predistorter [6]. The upper and lower lines pertain to the PD and SSPA model, respectively, and the solid line represents the compensated effect. It shows similar effect with soft envelop limiter.

3. Design Architecture

The closed form expression of predistorter output š‘ž is shown in the previous section. However, the information of HPA parameters š“0 and š‘ are unknown and time varying in practice. Figure 3 shows the detailed design of the architecture of our predistorter for a real time-varying environment.

The major block in the OFDM predistorter is an LMS block to update š“0 and š‘ estimations and š‘ž estimation block which will be explained next in detail. As for other supporting blocks, R/P (rectangular coordinates transfer to polar coordinates) and P/R (polar coordinates transfer to rectangular coordinates) are employed with a 12-stage cordic algorithm. A look-up table is used to store the precalculated values for the calculation of LMS update and š‘ž estimation.

3.1. LMS Update

The total period is divided into two stages: the training stage covers the start time and periodic pilot time, and the remaining time is the operation stage (see Figure 4).

During the training stage, š‘ž estimation block is off, that is, š‘ž is set to be equivalent to the input signal magnitude of š‘Ÿ, and correspondent HPA output š‘¢ is known. The goal during this stage is to track the solution of time-varying š“0 and š‘ by LMS algorithm. We define mean square error as follows:

š½ī€·š“0ī€øāŽ›āŽœāŽœāŽœāŽš‘ž,š‘=šøī‚€ī€·1+š‘ž/š“0ī€ø2š‘ī‚1/2š‘āŽžāŽŸāŽŸāŽŸāŽ āˆ’š‘¢2.(4)

From the appendix, we have the expressions of šœ•š½(š“0,š‘)/šœ•š“0 and šœ•š½(š“0,š‘)/šœ•š‘. For LMS algorithm, expected value is replaced by instantaneous value. Therefore, īš“0=īš“(š‘›+1)0(š‘›)āˆ’šœ‡1ā‹…āŽ”āŽ¢āŽ¢āŽ¢āŽ¢āŽ¢āŽ£āŽ›āŽœāŽœāŽœāŽœāŽœāŽš‘ž(š‘›)ī‚µī‚€īš“1+š‘ž(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶1/2Ģ‚š‘(š‘›)āŽžāŽŸāŽŸāŽŸāŽŸāŽŸāŽ ā‹…īƒ©āˆ’š‘¢(š‘›)š‘ž(š‘›)īš“0īƒŖ(š‘›)2Ģ‚š‘(š‘›)+1ā‹…āŽ›āŽœāŽœāŽœāŽœāŽœāŽ1ī‚µī‚€īš“1+(š‘ž(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶1/2Ģ‚š‘(š‘›)+1āŽžāŽŸāŽŸāŽŸāŽŸāŽŸāŽ āŽ¤āŽ„āŽ„āŽ„āŽ„āŽ„āŽ¦,Ģ‚š‘(š‘›+1)=Ģ‚š‘(š‘›)āˆ’šœ‡2ā‹…āŽ§āŽŖāŽŖāŽØāŽŖāŽŖāŽ©āŽ›āŽœāŽœāŽœāŽœāŽœāŽš‘ž(š‘›)ī‚µī‚€īš“1+š‘ž(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶1/2Ģ‚š‘(š‘›)āŽžāŽŸāŽŸāŽŸāŽŸāŽŸāŽ ā‹…āŽ›āŽœāŽœāŽœāŽœāŽœāŽāˆ’š‘¢(š‘›)š‘ž(š‘›)ī‚µī‚€īš“1+š‘ž(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶1/2Ģ‚š‘(š‘›)āŽžāŽŸāŽŸāŽŸāŽŸāŽŸāŽ ā‹…āŽ”āŽ¢āŽ¢āŽ¢āŽ¢āŽ£āŽ›āŽœāŽœāŽœāŽœāŽāˆ’1ī‚µī‚€īš“Ģ‚š‘(š‘›)ā‹…1+š‘ž(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶āŽžāŽŸāŽŸāŽŸāŽŸāŽ īƒ©ā‹…lnš‘ž(š‘›)īš“0īƒŖā‹…īƒ©(š‘›)š‘ž(š‘›)īš“0īƒŖ(š‘›)2Ģ‚š‘(š‘›)+ī‚µī‚€īš“ln1+š‘ž(š‘›)/0(š‘›)ī‚2Ģ‚š‘(š‘›)ī‚¶2Ģ‚š‘(š‘›)2āŽ¤āŽ„āŽ„āŽ„āŽ„āŽ¦āŽ«āŽŖāŽŖāŽ¬āŽŖāŽŖāŽ­,(5) where šœ‡1 and šœ‡2 are step factors which will be defined in the following section, and the initial settings are š“0(0)=1 and š‘(0)=1.

3.2. š‘ž Estimation

Figure 4 shows that after š‘1 samples in training stage, LMS is turned on once per š‘2 samples to update the estimates of š“0 and š‘, and turned off during the remaining time (operation stage). Within the operation stage, predistorter is on, and š‘ž estimation is calculated based on the LMS estimations of š“0 and š‘. That is, āŽ§āŽŖāŽŖāŽØāŽŖāŽŖāŽ©š‘ž(š‘›)=š‘Ÿ(š‘›)ī‚µī‚€īš“1āˆ’š‘Ÿ(š‘›)/0ī‚(š‘›)2Ģ‚š‘(š‘›)ī‚¶1/2Ģ‚š‘(š‘›)īš“,š‘Ÿ(š‘›)<0š‘ž(š‘›),maxīš“,š‘Ÿ(š‘›)ā‰„0(š‘›).(6) Please note that when īš“š‘Ÿ(š‘›)ā‰„0(š‘›), š‘ž(š‘›) is clipped to š‘žmax. In this paper, we set š‘žmax=8, which will be shown to be suitable in the numerical result session.

3.3. Look-up Table

Five sets of function results are required to be stored in the look-up table to calculate the following functions: š¹1(š‘„,š‘¦)=[š‘„2š‘¦/(1āˆ’š‘„2š‘¦)]1/2š‘¦, š¹2(š‘„)=ln(š‘„), š¹3(š‘„,š‘¦)=ln[1+š‘„2š‘¦], š¹4(š‘„,š‘¦)=[š‘„2š‘¦/1+š‘„2š‘¦]1/2š‘¦, and š¹5(š‘„,š‘¦)=š‘„2š‘¦/1+š‘„2š‘¦.

Nonlinear quantization is applied to save table space. As for š¹1(š‘„,š‘¦), š‘¦ is quantized to š‘š1/32 when 33ā‰¤š‘š1ā‰¤96; š‘„ is quantized to š‘š2/32 when 1ā‰¤š‘š2ā‰¤24, š‘š2/64 when 49ā‰¤š‘š2ā‰¤54, š‘š2/128 when 109ā‰¤š‘š2ā‰¤123, or š‘š2/256 when 247ā‰¤š‘š2ā‰¤255. Thus, table I requires the size of [64āˆ—(24+6+15+9)]Ɨ16=3456Ɨ16. As for š¹2(š‘„), š‘„ is quantized to š‘š/512 when 1ā‰¤š‘šā‰¤60, š‘š/256 when 61ā‰¤š‘šā‰¤120, š‘š/64 when 31ā‰¤š‘šā‰¤512 (š‘„ will be clipped as eight if it exceeds eight). Thus, table II requires the size of (60+60+482)Ɨ16=602Ɨ16. As for š¹3(š‘„,š‘¦), š‘¦ is quantized to š‘š1/32 when 33ā‰¤š‘š1ā‰¤96; š‘„ is quantized to š‘š2/32 when 1ā‰¤š‘š2ā‰¤31, š‘š2/16 when 16ā‰¤š‘š2ā‰¤31, š‘š2/8 when 16ā‰¤š‘š2ā‰¤64. Thus, table III requires the size of [64āˆ—(31+16+49)]Ɨ16=6144Ɨ16. As for š¹4(š‘„,š‘¦), š‘¦ is quantized to š‘š1/32 when 33ā‰¤š‘š1ā‰¤96; š‘„ is quantized to š‘š2/64 when 1ā‰¤š‘š2ā‰¤63, š‘š2/32 when 32ā‰¤š‘š2ā‰¤63, š‘š2/16 when 32ā‰¤š‘š2ā‰¤47, š‘š2/8 when 24ā‰¤š‘š2ā‰¤64. Thus, table IV requires the size of [64āˆ—(63+32+16+41)]Ɨ16=9728Ɨ16. As for š¹5(š‘„,š‘¦), š‘¦ is quantized to š‘š1/32 when 33ā‰¤š‘š1ā‰¤96; š‘„ is quantized to š‘š2/32 when 1ā‰¤š‘š2ā‰¤63, š‘š2/8 when 16ā‰¤š‘š2ā‰¤64. Thus, table V requires the size of [64āˆ—(63+49)]Ɨ16=6944Ɨ16. The total size for all of these five look-up tables is 26874Ɨ16 whose area is less than 0.5mm2 for CMOS18.

3.4. Complexity Evaluation

Based on the precalculated parameters, (5) can be expressed as īš“0īš“(š‘›+1)=0(š‘›)āˆ’šœ‡1ā‹…īš“īƒÆīƒ¬0(š‘›)ā‹…š¹4īƒ©š‘ž(š‘›)īš“0īƒŖīƒ­(š‘›),Ģ‚š‘(š‘›)āˆ’š‘¢(š‘›)ā‹…š¹4īƒ©š‘ž(š‘›)īš“0īƒŖ(š‘›),Ģ‚š‘(š‘›)ā‹…š¹4īƒ©š‘ž(š‘›)īš“0,(š‘›),Ģ‚š‘(š‘›)īƒŖīƒ°(7)Ģ‚š‘(š‘›+1)=Ģ‚š‘(š‘›)āˆ’šœ‡2ā‹…īš“īƒÆīƒ¬0(š‘›)ā‹…š¹4īƒ©š‘ž(š‘›)īš“0īƒŖīƒ­ā‹…īš“(š‘›),Ģ‚š‘(š‘›)āˆ’š‘¢(š‘›)0(š‘›)ā‹…š¹4īƒ©š‘ž(š‘›)īš“0īƒŖā‹…āŽ”āŽ¢āŽ¢āŽ£āˆ’š¹(š‘›),Ģ‚š‘(š‘›)4ī‚€īš“š‘ž(š‘›)/0ī‚(š‘›),Ģ‚š‘(š‘›)Ģ‚š‘(š‘›)ā‹…š¹2īƒ©š‘ž(š‘›)īš“0(īƒŖ+š¹š‘›)3ī‚€īš“š‘ž(š‘›)/0ī‚(š‘›),Ģ‚š‘(š‘›)2Ģ‚š‘2āŽ¤āŽ„āŽ„āŽ¦āŽ«āŽŖāŽ¬āŽŖāŽ­.(š‘›)(8) After HPA parameters š“0 and š‘ estimation, the š‘ž is estimated by īš“Ģ‚š‘ž(š‘›)=0(š‘›)ā‹…š¹1īƒ©š‘ž(š‘›)īš“0īƒŖ(š‘›),Ģ‚š‘(š‘›).(9) Therefore, the complexity in total includes 5 addition/subtracitons and 15 multiplications which are relative low.

4. Numerical Results

From (1), HPA results in a highly nonlinear situation with high input amplitude, and small distortions vice versa. Therefore, a relative level of power back off is required to reduce HPA distortion. Here, we define input back-off (IBO) as IBO=10log10īƒ©š“20š‘ƒinīƒŖ,(10) where š‘ƒin is input average power of OFDM signal. Next, we will perform the algorithmic level and hardware level (fixed-point) simulations, while the latter include all the distortion effects in hardware such as round-off error and coefficient quantization.

We set the simulation parameters as follows.

(i)16QAM modulated OFDM signal with 64-point IFFT are studied. (ii)The average input back-off power is 6.375ā€‰dB, if not being mentioned. (iii)The start training sequence is employed with a length of š‘1=160 training samples, and every training sample per š‘2=16 OFDM symbols is applied to the following sequence. (iv)š“0 and š‘ are both assumed to be Gaussian random numbers with mean of 1 and variance of 0.0025. (v)Step factor šœ‡1=1.5 in training stage and 0.5 in the operation stage, while šœ‡2 is set to be as much as six times of šœ‡1. (vi)The bit width of OFDM output š¼š‘„,š‘„š‘„, the bit width of DAC input š¼š‘¦,š‘„š‘¦, and ADC output are evaluated, since the former is limited by the area cost, and the latter is limited by DAC/ADC design. (vii)The channel is assumed as AWGN with variance of šœ‚0/2.

From Figure 5, it shows that the bit width of 10 is recommended for OFDM BB output, DAC input, and ADC output, since there is not much improvement to increase bit width beyond 10. The proposed implementation plan of predistorter is shown to improve system performance even including degradation effect from hardware.

5. Conclusion

In this paper, we have provided an implementation plan of the proposed predistorter in [6] to compensate the nonlinear distortion of SSPA. We used an LMS algorithm for time-varying environment, which we have shown to be capable of tracking SSPA parameters. Finally, a fixed-point simulation including hardware degradation factor was performed to verify the superior performance of the proposed implementation scheme.


A. Derivative of š½(š“0,š‘) w.r.t š“0


B. Derivative of š½(š“0,š‘) w.r.t š‘