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Journal of Electrical and Computer Engineering
Volume 2010, Article ID 463925, 4 pages
http://dx.doi.org/10.1155/2010/463925
Research Article

New RTD-Based General Threshold Gate Topologies and Application to Three-Input XOR Logic Gates

1Science and Research Branch, Islamic Azad University, Tehran, Iran
2Electrical and Computer Faculty, Shahid Beheshti University, Tehran, Iran

Received 4 August 2009; Accepted 10 November 2009

Academic Editor: Paul D. Franzon

Copyright © 2010 S. M. Mirhoseini et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. C. Pacha, U. Auer, C. Burwick et al., “Threshold logic circuit design of parallel adders using resonant tunneling devices,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 8, no. 5, pp. 558–572, 2000. View at Publisher · View at Google Scholar
  2. J. Núñez, J. M. Quintana, and M. J. Avedillo, “Limits to a correct operation in RTD-based ternary inverters,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), pp. 604–607, Seattle, Wash, USA, May 2008. View at Publisher · View at Google Scholar
  3. Y. Zheng, Novel RTD-based threshold logic design and verification, Master of Science Thesis in Computer Engineering, Department of Electrical and Computer Engineering, Virginia Polytechnic Institute and State University, Blacksburg, Va, USA, 2008.
  4. H. Pettenghi, M. J. Avedillo, and J. M. Quintana, “Using multi-threshold threshold gates in RTD-based logic design,” Microelectronics Journal, vol. 39, no. 2, pp. 241–247, 2008. View at Publisher · View at Google Scholar
  5. M. J. Avedillo, J. M. Quintana, and H. Pettenghi, “Logic models supporting the design of MOBILE-based RTD circuits,” in Proceedings of the 16th International Conference on Application-Specific Systems, Architecture and Processors (ASAP '05), pp. 254–259, Samos, Greece, July 2005.
  6. K. S. Berezowski, “Compact binary logic circuits design using negative differential resistance devices,” Electronics Letters, vol. 42, no. 16, pp. 902–903, 2006. View at Publisher · View at Google Scholar
  7. H. Pettenghi, M. J. Avedillo, and J. M. Quintana, “A novel contribution to the RTD-based threshold logic family,” in Proceedings of the IEEE International Symposium on Circuits and Systems (ISCAS '08), pp. 2350–2353, Seattle, Wash, USA, May 2008. View at Publisher · View at Google Scholar