Two New Families of Floating FDNR Circuits

Abstract

Two new configurations for realizing ideal floating frequency-dependent negative resistor elements (FDNR) are introduced. The proposed circuits are symmetrical and are realizable by four CCII or ICCII or a combination of both. Each configuration is realizable by eight different circuits. Simulation results are included to support the theory.

1. Introduction

The frequency-dependent negative resistor (FDNR) element was introduced by Bruton [1] and used in the realization of ladder filters. Using the operational amplifier (Op Amp) as the active element, Antoniou introduced several realizations of the current generalized impedance converter (CGIC) which was used in active network synthesis of voltage transfer functions [2]. The GIC can also be used in the realization of grounded and floating inductors or FDNR elements [3].

The current conveyor (CCII) [4] was used in realizing grounded and floating inductors and FDNR elements. The first realization in the literature for realizing an ideal grounded FDNR was reported in [5] and it employs a single CCII+, two capacitors, and four resistors, and it requires conditions on the magnitudes of the passive elements. The minimum number of passive elements to realize an ideal FDNR is two capacitors and one resistor. The circuits shown in Figure 1 fulfill this minimum passive element condition and realize an ideal floating FDNR and each circuit uses two; CCII+ and one CCII− [6, 7]. Two alternative realizations of the ideal FDNR using minimum passive components were introduced in [8] using two CCII and a buffer. The circuit shown in Figure 2(a) uses a CCII to realize the buffer and has the disadvantage that the capacitor 𝐶₁ is in series with 𝑅_𝑋3 and the capacitor 𝐶₂ is in series with 𝑅_𝑋2 thus limits the frequency of operation of the circuit [9]. The circuit shown in Figure 2(b) was also introduced in [8] and avoids the direct connection of a capacitor to the 𝑋 terminal of a CCII. Four more ideal floating FDNR circuits using two CCII and a negative impedance converter (NIC) were proposed in [10], two of them have capacitors connected to port 𝑋 of the CCII. The circuit shown in Figure 3(a) uses two; CCII+ and one CCII− and realizes ideal floating inductor by using 𝑌₁ and 𝑌₃ as resistors and 𝑌₂ as a capacitor [11]. The circuit can also be used to realize an ideal FDNR by taking 𝑌₁ as 𝐶₁, 𝑌₂ as 𝑅, and 𝑌₃ as 𝐶₂. In this case, however, the parasitic resistances 𝑅_𝑋1 and 𝑅_𝑋2 will act in series with 𝐶₂ and 𝐶₁, respectively, and degrades the circuit operation at high frequencies [9]. An alternative floating inductor circuit using three CCII and one CCI was given in [12], although the circuit can be modified using RC:CR transformation [3] to realize an ideal floating FDNR, the two capacitors will be connected to the 𝑋 terminals of two CCII which will affect the circuit operation as in the previous circuit.

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(b)

Figure 1 

(a) Floating FDNR circuit proposed in [6]. (b) Floating FDNR circuit proposed in [7].

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Figure 2 

(a) Floating FDNR circuit proposed in [8]. (b) Another floating FDNR circuit proposed in [8].

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Figure 3 

(a) Floating inductor circuit proposed in [11]. (b) Floating FDNR circuit proposed in [13]. (c) Floating FDNR circuit proposed in [14]. (d) Floating FDNR circuit proposed in [14].

A two CCII− realization of a floating FDNR was introduced in [13] and is shown in Figure 3(b). This realization uses two capacitors and three resistors that is, two resistors more than the minimum required number. The floating admittance realized is given by 𝑠𝑌=²𝐶₁𝐶₂𝑅₁𝑅₂𝑅₃. (1) Three more similar circuits were given in [14]; two of them are shown in Figures 3(c) and 3(d) and each realizes a floating FDNR whose admittance is given by (1).

The circuit shown in Figure 4(a) using four CCII+ realizing ideal floating inductor was introduced in [15]. The circuit is symmetrical and can also employ four CCII− as demonstrated in [16, 17]. Recently the circuit shown in Figure 4(a) is generated using nodal admittance matrix expansion [18] which can also lead to the generation of the circuit shown in Figure 4(b).

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(b)

Figure 4 

(a) Floating circuit 1 suitable for 𝐿 realization [15]. (b) Floating circuit 2 suitable for 𝐿 realization [15, 16].

Due to the connection of the two capacitors in series with the parasitic resistances 𝑅_𝑋 of the four CCII, the circuits shown in Figure 4 are not suitable for realizing floating FDNR.

In this paper, two new generalized circuit topologies suitable for floating FDNR realizations are introduced. The first proposed circuit is generated from the circuits of Figure 4 by interchanging ports 𝑋 and 𝑌 of the four CCII and then generalizing the circuit to employ CCII or inverting CCII [19] or a combination of both.

Other realizations for the floating FDNR using nullor [20] operational mirror amplifier [21, 22] and current feedback operational amplifier [23] are available in the literature.

2. Proposed FDNR Configurations

2.1. Generalized Conveyor

The building block that is used in this section is the generalized conveyor (GC) defined by the following matrix equation: 𝐼_𝑌𝑉_𝑋𝐼_𝑍=000𝑉𝐴000𝐾0^𝑌𝐼_𝑋𝑉_𝑍. (2) The parameter 𝐴 determines the type of the conveyor; a CCII is realized if 𝐴=1 and ICCII is obtained if 𝐴=−1.

The parameter 𝐾 determines the conveyor 𝑍 polarity; for 𝑍+ the parameter 𝐾=1 and for 𝑍− the parameter 𝐾=−1.

The GC includes four different types; the CCII− and the ICCII− are floating whereas the CCII+ and ICCII+ are not floating. The CCII+ and ICCII+ although nonfloating can also be used in realizing floating circuits provided they are used in pairs as will be demonstrated in the next section.

2.2. The First New Configuration

Figure 5(a) represents the first proposed generalized floating FDNR circuit. For floating operation, GC1 and GC2 must be identical and GC3 and GC4 must also be identical. It can be shown that the transmission matrix for the circuit of Figure 5(a) is given by 𝑉₁𝐼₁=1𝐴₁𝐾₁𝐴₃𝐾₃𝑠²𝐶₁𝐶₂𝑅𝑉01−𝐼²₂. (3) A necessary coefficient condition for realizing a floating FDNR is that 𝐴₁𝐾₁𝐴₃𝐾₃=1. (4) In this case, the transmission matrix given by (3) realizes a floating admittance given by 𝑌=𝑠²𝐶₁𝐶₂𝑅. (5) The coefficient condition given by (4) is satisfied by eight alternative realizations as given in Table 1.

Table 1 

Eight alternative conveyor circuits based on Figure 5(a).

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Figure 5 

(a) New floating circuit 1 suitable for FDNR realization. (b) New floating circuit 2 suitable for FDNR realization.

2.3. The Second New Configuration

Figure 5(b) represents the second proposed generalized floating FDNR circuit. For floating operation, GC1 and GC2 must be identical and GC3 and GC4 must also be identical. It can be shown that the transmission matrix for the circuit of Figure 5(b) is given by 𝑉₁𝐼₁=𝐴1−¹𝐾₁𝐴₃𝐾₃𝑠²𝐶₁𝐶₂𝑅𝑉01−𝐼²₂. (6) A necessary coefficient condition for realizing a floating FDNR is that 𝐴₁𝐾₁𝐴₃𝐾₃=−1. (7) In this case, the transmission matrix given by (6) realizes a floating admittance given by (5). The coefficient condition given by (7) is satisfied by eight alternative realizations as given in Table 2.

Table 2 

Eight alternative conveyor circuits based on Figure 5(b).

3. Simulation Results

The active building block used in the simulations is the differential voltage current conveyor (DVCC) shown in Figure 6 [24]; the MOS transistor aspect ratios are given in Table 3 based on the 0.5 𝜇m CMOS model from MOSIS. The supply voltages used are ±1.5 V, 𝑉_𝐵1=−0.52 V, and 𝑉_𝐵2=0.33 V. The Spice simulation results for two of the new FDNR circuits numbers 1 and 8 in Table 2 are shown in Figure 7.

Table 3 

Dimensions of the MOS Transistors of Figure 6.

Figure 6 

CMOS circuit of the DVCC used in the simulations [24].

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Figure 7 

(a) Frequency response of the FDNR realization 1 in Table 2. (b) Frequency response of the FDNR realization 8 in Table 2.

The FDNR circuit is designed by taking 𝐶₁=𝐶₂=10 pF and 𝑅=1 kΩ. The circuit is excited at port 1 by a current source of 1 mA, and port 2 is grounded. The frequency response of 𝑉₁ is shown in Figure 7(a) and the power dissipation is 3.79746 mW. The simulation are repeated by exciting port 2 by the current source and simulating 𝑉₂, an identical frequency response is obtained, which proves that the circuit is symmetrical as expected.

The simulation results for the circuit number 8 specified in Table 2 is shown in Figure 7(b) and the power dissipation is 4.00417 mW.

4. Discussion of Nonidealities

The main objective of the paper is to present new symmetrical circuits realizing floating FDNR circuits using minimum passive elements and avoiding the connection of the two capacitors to the 𝑋 terminals of the CCII or the ICCII.

It may be useful to discuss the nonidealities in the following subsections.

4.1. Voltage and Current Tracking Errors

There are non-idealities associated with typical CCII and ICCII devices represented in voltage and current tracking errors between the 𝑌 and 𝑋 terminals and the 𝑋 and 𝑍 terminals, respectively. These tracking errors show up as nonunity voltage and current gains between the 𝑌 and 𝑋 terminals and 𝑋 and 𝑍 terminals, respectively. The actual characteristics of the CCII or the ICCII can be represented by the following matrix equation: 𝐼_𝑌𝑉_𝑋𝐼_𝑍=000𝑉±(1−𝛼)000±(1−𝛽)0^𝑌𝐼_𝑋𝑉_𝑍. (8) The plus sign in the second row applies to CCII and the negative sign applies to ICCII. The plus sign in the third row applies to CCII+ or ICCII+ and the negative sign applies to CCII− or ICCII−, where 𝛼 and 𝛽 are the voltage and current tracking errors and are very small compared to unity. The actual values of 𝛼 and 𝛽 depend on the actual implementation of the CCII and the ICCII.

Taking these errors into consideration and assuming a symmetrical circuit, GC1 and GC2 are matched and GC3 and GC4 are also matched; the actual value of the magnitude of the FDNR can be obtained as 𝐶𝐷=¹𝐶₂𝑅(1−𝛼₁)(1−𝛼₃)(1−𝛽₁)(1−𝛽₃). (9) Assume equal alphas and betas, the above equation is simplified to 𝐷=𝐶₁𝐶₂𝑅(1+2𝛼₁+2𝛽₁). (10)

4.2. Effect of Parasitic Elements

According to the CCII or ICCII model, we include the parasitic elements that are mainly represented by the 𝑋 terminal resistance 𝑅_𝑋 and the Z terminal capacitance 𝐶_𝑍.

The effect of the parasitic resistances 𝑅_𝑋3 and 𝑅_𝑋4 acting in series with the resistor 𝑅 is to increase the magnitude of the FDNR value to be 𝐷=𝐶₁𝐶₂(𝑅+𝑅_𝑋3+𝑅_𝑋4). (11) This effect can be internally compensated by reducing the value of the resistor 𝑅 by (𝑅_𝑋3+𝑅_𝑋4).

The effect of the parasitic resistances 𝑅_𝑋1 and 𝑅_𝑋2 is to add a series resistance to the realizable FDNR equal to 𝑅_𝑋1+𝑅_𝑋2. This cannot be internally compensated; however, external compensation is possible using an active negative resistor of same value in series with the FDNR circuit. The two capacitors provided by the 𝑍 terminals of the GC1and GC2 will appear at the two nodes of the capacitor 𝐶₂ and their effect can be minimized by taking large value of 𝐶₂.

Similarly, the two capacitors provided by the 𝑍 terminals of the GC3 and GC4 will appear at the two nodes of the capacitor 𝐶₁ and their effect can be minimized by taking large value of 𝐶₁.

5. Conclusions

A review of early published floating FDNR circuits using CCII is given. A new floating FDNR circuit using a CCII− and two ICCII− is derived from the well-known circuit of Figure 1(b) and is shown in Figure 8.

Figure 8 

Floating FDNR realization using one CCII− and two ICCII−.

Two new configurations for realizing ideal floating FDNR are introduced. The proposed circuits are symmetrical and are realizable by four CCII or ICCII or combination of both. Each configuration is realizable by eight different circuits. The main advantage of the proposed circuits is avoiding the capacitors to be connected to the 𝑋 terminals of the CCII or ICCII. Simulation results are included to support the theory.