Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2011, Article ID 507381, 12 pages
http://dx.doi.org/10.1155/2011/507381
Review Article

Open-Loop Wide-Bandwidth Phase Modulation Techniques

1Electrical Engineering Department, University of California, Los Angeles, CA 90095-1594, USA
2Broadcom Corporation, Irvine, CA 92617-3038, USA

Received 31 May 2011; Accepted 16 August 2011

Academic Editor: Kenichi Okada

Copyright © 2011 Nitin Nidhi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. V. Petrovic and W. Gosling, “Polar-loop transmitter,” Electronics Letters, vol. 15, no. 10, pp. 286–288, 1979. View at Google Scholar · View at Scopus
  2. M. R. Elliott, T. Montalvo, B. P. Jeffries et al., “A polar modulator transmitter for GSM/EDGE,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2190–2199, 2004. View at Publisher · View at Google Scholar · View at Scopus
  3. T. Sowlati, D. Rozenblit, R. Pullela et al., “Quad-band GSM/GPRS/EDGE polar loop transmitter,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2179–2189, 2004. View at Publisher · View at Google Scholar · View at Scopus
  4. A. W. Hietala, “A quad-band 8PSK/GMSK polar transceiver,” IEEE Journal of Solid-State Circuits, vol. 41, no. 5, pp. 1133–1141, 2006. View at Publisher · View at Google Scholar · View at Scopus
  5. Y. Akamine, S. Tanaka, M. Kawabe et al., “A polar loop transmitter with digital interface including a loop-bandwidth calibration system,” in Proceedings of the IEEE International Solid-State Circuits Conference: Digest of Technical Papers (ISSCC '07), pp. 348–349, San Francisco, Calif, USA, February 2007. View at Publisher · View at Google Scholar
  6. D. C. Cox, “Linear amplification with nonlinear components,” IEEE Transactions on Communications, vol. 22, no. 12, pp. 1942–1945, 1974. View at Google Scholar · View at Scopus
  7. M. E. Heidari, M. Lee, and A. A. Abidi, “All-digital outphasing modulator for a software-defined transmitter,” IEEE Journal of Solid-State Circuits, vol. 44, no. 4, Article ID 4804977, pp. 1260–1271, 2009. View at Publisher · View at Google Scholar · View at Scopus
  8. T. A. D. Riley and M. A. Copeland, “A simplified continuous phase modulator technique,” IEEE Transactions on Circuits and Systems II: Analog and Digital Signal Processing, vol. 41, no. 5, pp. 321–328, 1994. View at Publisher · View at Google Scholar · View at Scopus
  9. N. M. Filiol, T. A. D. Riley, C. Plett, and M. A. Copeland, “An agile ISM band frequency synthesizer with built-in GMSK data modulation,” IEEE Journal of Solid-State Circuits, vol. 33, no. 7, pp. 998–1008, 1998. View at Google Scholar · View at Scopus
  10. S. Pamarti, L. Jansson, and I. Galton, “A wideband 2.4-GHz delta-sigma fractional-N PLL with 1-Mb/s in-loop modulation,” IEEE Journal of Solid-State Circuits, vol. 39, no. 1, pp. 49–62, 2004. View at Publisher · View at Google Scholar · View at Scopus
  11. M. H. Perrott, T. L. Tewksbury III, and C. G. Sodini, “A 27-mW CMOS fractional-N synthesizer using digital compensation for 2.5-Mb/s GFSK modulation,” IEEE Journal of Solid-State Circuits, vol. 32, no. 12, pp. 2048–2059, 1997. View at Google Scholar · View at Scopus
  12. M. Youssef, A. Zolfaghari, H. Darabi, and A. Abidi, “A low-power wideband polar transmitter for 3G applications,” in Proceedings of the IEEE International Solid-State Circuits Conference: Digest of Technical Papers (ISSCC '11), pp. 378–379, San Francisco, Calif, USA, February 2011. View at Publisher · View at Google Scholar
  13. R. B. Staszewski, J. L. Wallberg, S. Rezeq et al., “All-digital PLL and transmitter for mobile phones,” IEEE Journal of Solid-State Circuits, vol. 40, no. 12, pp. 2469–2482, 2005. View at Publisher · View at Google Scholar · View at Scopus
  14. S. A. Yu and P. Kinget, “A 0.65-V 2.5-GHz fractional-N synthesizer with two-point 2-Mb/s GFSK data modulation,” IEEE Journal of Solid-State Circuits, vol. 44, no. 9, Article ID 5226689, pp. 2411–2425, 2009. View at Publisher · View at Google Scholar · View at Scopus
  15. W. W. Si, D. Weber, S. Abdollahi-Alibeik et al., “A single-chip CMOS bluetooth v2.1 radio SoC,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, Article ID 4684630, pp. 2896–2904, 2008. View at Publisher · View at Google Scholar · View at Scopus
  16. K. C. Peng, C. H. Huang, C. J. Li, and T. S. Horng, “High-performance frequency-hopping transmitters using two-point delta-sigma modulation,” IEEE Transactions on Microwave Theory and Techniques, vol. 52, no. 11, pp. 2529–2535, 2004. View at Publisher · View at Google Scholar · View at Scopus
  17. S. Lee, J. Lee, H. Park, K. Y. Lee, and S. Nam, “Self-calibrated two-point delta-sigma modulation technique for RF transmitters,” IEEE Transactions on Microwave Theory and Techniques, vol. 58, no. 7, Article ID 5481987, pp. 1748–1757, 2010. View at Publisher · View at Google Scholar · View at Scopus
  18. Y. H. Liu and T. H. Lin, “A wideband PLL-based G/FSK transmitter in 0.18 μm CMOS,” IEEE Journal of Solid-State Circuits, vol. 44, no. 9, Article ID 5226692, pp. 2452–2462, 2009. View at Publisher · View at Google Scholar · View at Scopus
  19. H. Mair and L. Xiu, “Architecture of high-performance frequency and phase synthesis,” IEEE Journal of Solid-State Circuits, vol. 35, no. 6, pp. 835–846, 2000. View at Publisher · View at Google Scholar · View at Scopus
  20. P. E. Su and S. Pamarti, “A 2.4 GHz wideband open-loop GFSK transmitter with phase quantization noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 46, no. 3, pp. 615–626, 2011. View at Publisher · View at Google Scholar
  21. P. Y. Wang, J. H. C. Zhan, H. H. Chang, and H. M. S. Chang, “A digital intensive fractional-N PLL and all-digital self-calibration schemes,” IEEE Journal of Solid-State Circuits, vol. 44, no. 8, Article ID 5173739, pp. 2182–2192, 2009. View at Publisher · View at Google Scholar · View at Scopus
  22. K. J. Wang, A. Swaminathan, and I. Galton, “Spurious tone suppression techniques applied to a wide-bandwidth 2.4 GHz fractional-N PLL,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, Article ID 4684634, pp. 2787–2797, 2008. View at Publisher · View at Google Scholar · View at Scopus
  23. E. Temporiti, G. Albasini, I. Bietti, and R. Castello, “A 700-kHz bandwidth ΣΔ fractional synthesizer with spurs compensation and linearization techniques for WCDMA applications,” IEEE Journal of Solid-State Circuits, vol. 39, no. 9, pp. 1446–1454, 2004. View at Publisher · View at Google Scholar · View at Scopus
  24. M. Gupta and B. S. Song, “A 1.8-GHz spur-cancelled fractional-N frequency synthesizer with LMS-based DAC gain calibration,” IEEE Journal of Solid-State Circuits, vol. 41, no. 12, pp. 2842–2851, 2006. View at Publisher · View at Google Scholar · View at Scopus
  25. A. Swaminathan, K. J. Wang, and I. Galton, “A wide-bandwidth 2.4 GHz ISM-band fractional-N PLL with adaptive phase-noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 42, no. 12, pp. 2639–2650, 2007. View at Publisher · View at Google Scholar
  26. S. E. Meninger and M. H. Perrott, “A 1-MHZ bandwidth 3.6-GHz 0.18-μm CMOS fractional-N synthesizer utilizing a hybrid PFD/DAC structure for reduced broadband phase noise,” IEEE Journal of Solid-State Circuits, vol. 41, no. 4, pp. 966–980, 2006. View at Publisher · View at Google Scholar · View at Scopus
  27. P. E. Su and S. Pamarti, “A 2-MHz bandwidth Δ—Σ fractional-N synthesizer based on a fractional frequency divider with digital spur suppression,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC '10), pp. 413–416, Anaheim, Calif, USA, May 2010. View at Publisher · View at Google Scholar · View at Scopus
  28. H. Hedayati, W. Khalil, and B. Bakkaloglu, “A 1 MHz bandwidth, 6 GHz 0.18 μm CMOS type-I δσ fractional-N synthesizer for WiMAX applications,” IEEE Journal of Solid-State Circuits, vol. 44, no. 12, Article ID 5342360, pp. 3244–3252, 2009. View at Publisher · View at Google Scholar · View at Scopus
  29. M. Nilsson, S. Mattisson, N. Klemmer et al., “A 9-band WCDMA/EDGE transceiver supporting HSPA evolution,” in Proceedings of the IEEE International Solid-State Circuits Conference: Digest of Technical Papers (ISSCC '11), pp. 366–367, San Francisco, Calif, USA, February 2011. View at Publisher · View at Google Scholar
  30. C. M. Hsu, M. Z. Straayer, and M. H. Perrott, “A low-noise wide-BW 3.6-GHz digital ΔΣ fractional-N frequency synthesizer with a noise-shaping time-to-digital converter and quantization noise cancellation,” IEEE Journal of Solid-State Circuits, vol. 43, no. 12, Article ID 4684627, pp. 2776–2786, 2008. View at Publisher · View at Google Scholar · View at Scopus
  31. M. Lee, M. E. Heidari, and A. A. Abidi, “A low-noise wideband digital phase-locked loop based on a coarse-fine time-to-digital converter with subpicosecond resolution,” IEEE Journal of Solid-State Circuits, vol. 44, no. 10, pp. 2808–2816, 2009. View at Publisher · View at Google Scholar · View at Scopus
  32. M. Zanuso, S. Levantino, C. Samori, and A. Lacaita, “A 3MHz-BW 3.6 GHz digital fractional-N PLL with sub-gate-delay TDC, phase-interpolation divider, and digital mismatch cancellation,” in Proceedings of the IEEE International Solid-State Circuits Conference: Digest of Technical Papers (ISSCC '10), pp. 476–477, San Francisco, Calif, USA, February 2010. View at Publisher · View at Google Scholar · View at Scopus
  33. R. B. Staszewski, K. Muhammad, D. Leipold et al., “All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS,” IEEE Journal of Solid-State Circuits, vol. 39, no. 12, pp. 2278–2291, 2004. View at Publisher · View at Google Scholar · View at Scopus
  34. T. LaRocca, J. Liu, F. Wang, and F. Chang, “Embedded DiCAD linear phase shifter for 57–65 GHz reconfigurable direct frequency modulation in 90nm CMOS,” in Proceedings of the IEEE Radio Frequency Integrated Circuits Symposium (RFIC '09), pp. 219–222, Boston, Mass, USA, June 2009. View at Publisher · View at Google Scholar · View at Scopus
  35. Delta-SigmaToolBox, http://www.mathworks.com/matlabcentral/fileexchange/19.