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Journal of Electrical and Computer Engineering
Volume 2011 (2011), Article ID 670508, 6 pages
Research Article

New Low-Power Tristate Circuits in Positive Feedback Source-Coupled Logic

1Electronics and Communication Department, Delhi Technological University, New Delhi, India
2Electronics and Communication Division, Netaji Subhas Institute of Technology, New Delhi, India

Received 31 March 2011; Revised 29 June 2011; Accepted 24 July 2011

Academic Editor: Mohamad Sawan

Copyright © 2011 Kirti Gupta et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Two new design techniques to implement tristate circuits in positive feedback source-coupled logic (PFSCL) have been proposed. The first one is a switch-based technique while the second is based on the concept of sleep transistor. Different tristate circuits based on both techniques have been developed and simulated using 0.18 μm CMOS technology parameters. A performance comparison indicates that the tristate PFSCL circuits based on sleep transistor technique are more power efficient and achieve the lowest power delay product in comparison to CMOS-based and the switch-based PFSCL circuits.