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Journal of Electrical and Computer Engineering
Volume 2011, Article ID 871385, 11 pages
Research Article

An Interpolated Flying-Adder-Based Frequency Synthesizer

Department of Computer and Communication Engineering, National Kaoshiung First University of Science and Technology, No. 2, Jhuoyue Road, Nanzih District, Kaohsiung City 811, Taiwan

Received 8 June 2011; Revised 25 August 2011; Accepted 25 August 2011

Academic Editor: Jae-Yoon Sim

Copyright © 2011 Pao-Lung Chen and Chun-Chien Tsai. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Citations to this Article [4 citations]

The following is the list of published articles that have cited the current article.

  • Pao-Lung Chen, “A low-cost carry look-ahead adder for flying-adder frequency synthesizer,” 2016 IEEE International Conference on Consumer Electronics-Taiwan (ICCE-TW), pp. 1–2, . View at Publisher · View at Google Scholar
  • Kusum Lata, and Manoj Kumar, “ADPLL design and implementation on FPGA,” 2013 International Conference on Intelligent Systems and Signal Processing, ISSP 2013, pp. 272–277, 2013. View at Publisher · View at Google Scholar
  • Pao-Lung Chen, and Chi-Hsin Cheng, “A fractional pseudo random binary sequence for spur reduction in flying-adder frequency synthesizer,” ISEEE 2014 - Proceedings: 2014 International Conference on Information Science, Electronics and Electrical Engineering, vol. 1, pp. 241–244, 2014. View at Publisher · View at Google Scholar
  • Pao-Lung Chen, Da-Chen Lee, and Wei-Chia Li, “Flying-Adder Frequency Synthesizer with a Novel Counter-Based Randomization Method,” Ieice Transactions On Electronics, vol. E98C, no. 6, pp. 480–488, 2015. View at Publisher · View at Google Scholar