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Journal of Electrical and Computer Engineering
Volume 2012, Article ID 267247, 17 pages
Research Article

480 MHz 10-tap Clock Generator Using Edge-Combiner DLL for USB 2.0 Applications

1Hitachi Central Research Laboratory, 1-280, Higashi-Koigakubo Kokubunji-shi, Tokyo 185-8601, Japan
2Technology Development Unit, Mixed Signal Core Development Division, Converter Development Department, Renesas Electronics Corporation, 4-1 Mizuhara, Itani-shi, Hyogo 664-0005, Tokyo, Japan
3SoC Business Unit, 1st Industry & Network Business Division, Optical Disc Solutions Department, Renesas Electronics Corporation, 5-20-1 Josuihon-cho, Kodaira-shi, Tokyo 187-8588, Japan

Received 28 June 2011; Accepted 8 September 2011

Academic Editor: Woogeun Rhee

Copyright © 2012 Takashi Kawamoto et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A clock generator with an edge-combiner DLL (ECDLL) has been developed for USB 2.0 applications. The clock generator generates 480 MHz 10-tap output signals from a 12 MHz reference signal and consists of three DLLs to shrink the design area so that it is smaller than a conventional one based on a PLL. Each DLL is applied to our proposed shot pulse reset technique to prevent from a harmonic lock and is applied to a voltage-controlled delay line (VCDL) with a trimming function to operate against any process voltage temperature (PVT) variations. A 90 nm CMOS process was used to fabricate our proposed clock generator. The 480 MHz 10-tap output signals satisfy the USB 2.0 specifications. A power consumption is less than 1.3 mW and a locking time is less than 3.5 μs, which are far less than a conventional one, 10.0 μs. The design area is 2 0 0 × 2 2 5 μm, which is half that of the conventional one.