Research Article

Improved Maximum Likelihood S-FSK Receiver for PLC Modem in AMR

Table 2

Memory and processing time analysis results for the PLC-modem DSP implementation.

ModulePM space
(16-bit Word)
DM space
(16-bit Word)
Number of cycles
machine during

Modulator module16206563840
ADC reception module10661601280
Correlation module2466562560
S-FSK decision module 8732156
Initialization PHY module513102323
PHY layer FSM module38698225236