Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs

<table class="table-group" width="800px"><tr class="fig-image" id="a"><td><img alt="484962.fig.009a" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.009a.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(a) </b>MPEG-4 SP decoder</td></tr></table></td></tr><tr class="fig-image" id="b"><td><img alt="484962.fig.009b" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.009b.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(b) </b>2-core partitioning</td></tr></table></td></tr><tr class="fig-image" id="c"><td><img alt="484962.fig.009c" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.009c.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(c) </b>3-core partitioning</td></tr></table></td></tr><tr class="fig-image" id="d"><td><img alt="484962.fig.009d" src="https://static.hindawi.com/articles/jece/volume-2012/484962/figures/484962.fig.009d.jpg"/></td></tr><tr class="fig-caption"><td align="center"><table><tr><td><b>(d) </b>4-core partitioning</td></tr></table></td></tr></table>

<table>Partitions of the parallel version of the MPEG-4 SP decoder for the 1, 2, 3, and 4 cores configurations.</table>

Journal of Electrical and Computer Engineering

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Figure 9

Figure 9: Hardware and Software Synthesis of Heterogeneous Systems from Dataflow Programs 