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Journal of Electrical and Computer Engineering
Volume 2012 (2012), Article ID 537286, 12 pages
http://dx.doi.org/10.1155/2012/537286
Research Article

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

1Indian Institute of Technology Madras, Chennai 600036, India
2iNoCs, 1007 Lausanne, Switzerland
3University of Bologna, 40138 Bologna, Italy
4EPFL, 1015 Lausanne, Switzerland

Received 17 July 2011; Accepted 1 November 2011

Academic Editor: An-Yeu Andy Wu

Copyright © 2012 Anish S. Kumar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Abstract

Buffers in on-chip networks constitute a significant proportion of the power consumption and area of the interconnect, and hence reducing them is an important problem. Application-specific designs have nonuniform network utilization, thereby requiring a buffer-sizing approach that tackles the nonuniformity. Also, congestion effects that occur during network operation need to be captured when sizing the buffers. Many NoCs are designed to operate in multiple voltage/frequency islands, with interisland communication taking place through frequency converters. To this end, we propose a two-phase algorithm to size the switch buffers in network-on-chips (NoCs) considering support for multiple-frequency islands. Our algorithm considers both the static and dynamic effects when sizing buffers. We analyze the impact of placing frequency converters (FCs) on a link, as well as pack and send units that effectively utilize network bandwidth. Experiments on many realistic system-on-Chip (SoC) benchmark show that our algorithm results in 42% reduction in amount of buffering when compared to a standard buffering approach.