Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2012, Article ID 537286, 12 pages
http://dx.doi.org/10.1155/2012/537286
Research Article

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

1Indian Institute of Technology Madras, Chennai 600036, India
2iNoCs, 1007 Lausanne, Switzerland
3University of Bologna, 40138 Bologna, Italy
4EPFL, 1015 Lausanne, Switzerland

Received 17 July 2011; Accepted 1 November 2011

Academic Editor: An-Yeu Andy Wu

Copyright © 2012 Anish S. Kumar et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. L. Benini and G. De Micheli, “Networks on chips: a new SoC paradigm,” Computer, vol. 35, no. 1, pp. 70–78, 2002. View at Publisher · View at Google Scholar
  2. G. D. Micheli and L. Benini, Networks on Chips: Technology and Tools, Morgan Kaufmann, 2006.
  3. P. Guerrier and A. Greiner, “A generic architecture for on-chip packet switched interconnections,” in Proceedings of the Design, Automation and Test in Europe, pp. 250–256, 2000.
  4. R. W. Apperson, Z. Yu, M. J. Meeuwsen, T. Mohsenin, and B. M. Baas, “A scalable dual-clock FIFO for data transfers between arbitrary and haltable clock domains,” IEEE Transactions on Very Large Scale Integration Systems, vol. 15, no. 10, pp. 1125–1134, 2007. View at Publisher · View at Google Scholar · View at Scopus
  5. A. Strano, D. Ludovici, and D. Bertozzi, “A library of dualclock fifos for cost-effective and flexible mpsoc design,” in Proceedings of the International Conference on Embedded Computer Systems (SAMOS '10), pp. 20–27, 2010.
  6. S. Murali, T. Theocharides, N. Vijaykrishnan, M. J. Irwin, L. Benini, and G. De Micheli, “Analysis of error recovery schemes for networks on chips,” IEEE Design and Test of Computers, vol. 22, no. 5, pp. 434–442, 2005. View at Publisher · View at Google Scholar · View at Scopus
  7. J. Hu and R. Marculescu, “Exploiting the routing flexibility for energy/performance aware mapping of regular NoC architectures,” in Proceedings of the Design, Automation and Test in Europe, 2004.
  8. A. Hansson et al., “A unified approach to mapping and routing in a combined guaranteed service and best-effort Network-on-Chip architecture,” in Proceedings of the International Conference on Hardware/Software Codesign and System Synthesis, 2005.
  9. S. Murali, P. Meloni, F. Angiolini et al., “Designing application-specific networks on chips with floorplan information,” in Proceedings of the International Conference on Computer-Aided Design (ICCAD '06), pp. 355–362, November 2006. View at Publisher · View at Google Scholar · View at Scopus
  10. J. Hu and R. Marculescu, “Application-specific buffer space allocation for networks-on-chip router design,” in Proceedings of the IEEE/ACM International Conference on Computer-Aided Design, Digest of Technical Papers (ICCAD '04), pp. 354–361, November 2004. View at Scopus
  11. Y. Yin and S. Chen, “An application-specific buffer allocation algorithm for network-on-chip,” in Proceedings of the 8th IEEE International Conference on ASIC (ASICON '09), pp. 439–442, October 2009. View at Publisher · View at Google Scholar · View at Scopus
  12. W. H. Ho and T. M. Pinkston, “A methodology for designing efficient On-Chip interconnects on well-behaved communication patterns,” in Proceedings of the International Symposium on High Performance Computer Architecture, 2003.
  13. J. Kong, J. Choi, L. Choi, and S. W. Chung, “Low-cost application-aware DVFS for multi-core architecture,” in Proceedings of the 3rd International Conference on Convergence and Hybrid Information Technology (ICCIT '08), pp. 106–111, November 2008. View at Publisher · View at Google Scholar · View at Scopus
  14. T. Kolpe, A. Zhai, and S. Sapatnekar, “Enabling improved power management in multicore processors through clustered dvfs,” in Proceedings of the Design, Automation Test in Europe Conference Exhibition (DATE '11), pp. 1–6, March 2011.
  15. S. Garg, D. Marculescu, R. Marculescu, and U. Ogras, “Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective,” in Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC '09), pp. 818–821, July 2009. View at Scopus
  16. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, “NoC topology synthesis for supporting shutdown of voltage islands in SoCs,” in Proceedings of the 46th ACM/IEEE Design Automation Conference (DAC '09), pp. 822–825, July 2009. View at Scopus
  17. L. Guang, E. Nigussie, and H. Tenhunen, “Run-time communication bypassing for energy-efficient, low-latency per-core dvfs on network-on-chip,” in Proceedings of the SOC Conference, pp. 481–486, September 2010.
  18. T. Jain, P. Gratz, A. Sprintson, and G. Choi, “Asynchronous bypass channels: improving performance for multisynchronous nocs,” in Proceedings of the 4th ACM/IEEE International Symposium on Networks-on-Chip (NOCS '10), pp. 51–58, May 2010.
  19. W. Liwei, C. Yang, L. Xiaohui, and Z. Xiaohu, “Application specific buffer allocation for wormhole routing Networkson-Chip,” Network on Chip Architectures, pp. 37–42, 2008. View at Google Scholar
  20. M. A. Al Faruque and J. Henkel, “Minimizing virtual channel buffer for routers in on-chip communication architectures,” in Proceedings of the Design, Automation and Test in Europe (DATE '08), pp. 1238–1243, March 2008. View at Publisher · View at Google Scholar · View at Scopus
  21. S. Yin, L. Liu, and S. Wei, “Optimizing buffer usage for networks-on-chip design,” in Proceedings of the International Conference on Communications, Circuits and Systems (ICCCAS '09), pp. 981–985, July 2009. View at Scopus
  22. N. Alzeidi, M. Ould-Khaoua, L. M. Mackenzie, and A. Khonsari, “Performance analysis of adaptively-routed wormhole-switched networks with finite buffers,” in Proceedings of the IEEE International Conference on Communications (ICC '07), pp. 38–43, June 2007. View at Publisher · View at Google Scholar · View at Scopus
  23. S. Foroutan, Y. Thonnart, R. Hersemeule, and A. Jerraya, “An analytical method for evaluating network-on-chip performance,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '10), pp. 1629–1632, March 2010. View at Scopus
  24. S. Manolache, P. Eles, and Z. Peng, “Buffer space optimisation with communication synthesis and traffic shaping for NoCs,” in Proceedings of the Design, Automation and Test in Europe ( DATE '06), pp. 718–723, March 2006. View at Scopus
  25. M. Coenen, S. Murali, A. Ruadulescu, K. Goossens, and G. De Micheli, “A buffer-sizing algorithm for networks on chip using TDMA and credit-based end-to-end flow control,” in Proceedings of the 4th International Conference on Hardware Software Codesign and System Synthesis, pp. 130–135, October 2006. View at Publisher · View at Google Scholar · View at Scopus
  26. A. B. Kahng, B. Lin, K. Samadi, and R. S. Ramanujam, “Trace-driven optimization of networks-on-chip configurations,” in Proceedings of the 47th Design Automation Conference (DAC '10), pp. 437–442, June 2010. View at Publisher · View at Google Scholar · View at Scopus
  27. S. Murali, M. Coenen, A. Radulescu, K. Goossens, and G. De Micheli, “A methodology for mapping multiple use-cases onto networks on chips,” in Proceedings of the Design, Automation and Test in Europe (DATE '06), pp. 118–123, March 2006. View at Scopus
  28. E. Beigne and P. Vivet, “Design of On-chip and Off-chip interfaces for a GALS NoC architecture,” in Proceedings of the International Symposium on Asynchronous Circuits and Systems (ASYNC ’06), pp. 172–183, IEEE Computer Society, Washington, DC, USA, 2006.
  29. W. J. Dally and B. Towels, Principles and Practices of Interconnection Networks, Morgan Kaufmann, 2003.
  30. Lp solve, http://lpsolve.sourceforge.net/.
  31. C. Seiculescu, S. Murali, L. Benini, and G. De Micheli, “SunFloor 3D: a tool for networks on chip topology synthesis for 3D systems on chips,” in Proceedings of the Design, Automation and Test in Europe Conference and Exhibition (DATE '09), pp. 9–14, April 2009. View at Scopus