Journal of Electrical and Computer Engineering

Research Article

A Buffer-Sizing Algorithm for Network-on-Chips with Multiple Voltage-Frequency Islands

Table 1

Network parameters.
Parameter Description
𝑉 Set of IP cores
𝑃 Set of NoC switches
𝐷 Set of frequencies of VF islands
𝐹 Set of flows in the network
F C _ l a t Latency of frequency converter
l e n g t h 𝑖 , 𝑗 length of link in m m
𝑁 𝑖 , 𝑗 Link latency in cycles
𝑈 𝑖 , 𝑗 Link utilization
𝛽 𝑖 , 𝑗 Buffer size at link 𝑞 𝑖 , 𝑗
p s 𝑘 Packet size of flow 𝑘
L C 𝑘 Latency constraint of flow 𝑘