A State-Based Modeling Approach for Efficient Performance Evaluation of Embedded System Architectures at Transaction Level

Table 4

Time constraints applied for each activity according to architectures.

Architecture	TCOFDMDemod	TCChanEstim	TCEqualizer	TCTurboDecoder
I	0,2*TC𝑃1	0,12*TC𝑃1	0,04*TC𝑃1	0,08*TC𝑃1
II	71428 ns	14285 ns	14285 ns	7142 ns