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Journal of Electrical and Computer Engineering
Volume 2012, Article ID 561580, 12 pages
Research Article

An Optimization Mechanism Intended for Static Power Reduction Using Dual- 𝑉 t h Technique

Informatics Center, Federal University of Pernambuco, Aveinda Jornalista Aníbal Fernandes, Cidade Universitária, 50670-901 Recife, PE, Brazil

Received 16 July 2011; Accepted 14 September 2011

Academic Editor: Dhireesha Kudithipudi

Copyright © 2012 Rodolfo P. Santos et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. N. S. Kim, T. Austin, D. Blaauw et al., “Leakage current: Moore's law meets static power,” IEEE Computer Society, vol. 36, no. 12, pp. 68–75, 2003. View at Publisher · View at Google Scholar
  2. International Technology Roadmap for Semiconductors (ITRS). 2008,
  3. D. Lee, D. Blaauw, and D. Sylvester, “Gate oxide leakage current analysis and reduction for VLSI circuits,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 12, no. 2, pp. 155–166, 2004. View at Publisher · View at Google Scholar
  4. J. C. Chi, H. H. Lee, S. H. Tsai, and M. C. Chi, “Gate level multiple supply voltage assignment algorithm for power optimization under timing constraint,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 15, no. 6, pp. 637–648, 2007. View at Publisher · View at Google Scholar
  5. A. G. Silva-Filho and S. M. L. Lima, “Energy consumption reduction mechanism by tuning cache configuration using nios II processor,” in Proceedings of the IEEE International SoC Conference (SOCC '08), pp. 291–294, Newport Beach, Calif, USA, 2008. View at Publisher · View at Google Scholar
  6. A. G. Silva-Filho, F. R. Cordeiro, R. E. Sant'anna, and M. E. Lima, “Heuristic for two-level cache hierarchy exploration considering energy consumption and performance,” in Proceedings of the Integrated Circuit and System Design. Power and Timing Modeling, Optimization, and Simulation (PATMOS '06), pp. 75–83, Montpellier, France, 2006.
  7. M. Pedram and J. M. Rabaey, Power Aware Design Methodology, Kluwer Academic, Boston, Mass, USA, 2002.
  8. M. Keating, D. Flynn, R. Aitken, A. Gibbons, and K. Shi, Low Power Methodology Manual for System-on-Chip Design, Springer, London, UK, 2007.
  9. M. Ketkar and S. S. Sapatnekar, “Standby power optimization via transistor sizing and dual threshold voltage assignment,” in Proceedings of the IEEE/ACM International Conference on Computer Aided Design (ICCAD '02), pp. 375–378, San Jose, Calif, USA, 2002. View at Publisher · View at Google Scholar · View at Scopus
  10. F. Brglez and H. Fujiwara, “A neural netlist of 10 combinational benchmark circuit and a target transistor in fortran,” in Proceedings of the International Symposium on Circuits and Systems, pp. 663–398, Kyoto, Japan, 1985.
  11. D. Lee and D. Blaauw, “Static leakage reduction through simultaneous threshold voltage and state assignment,” in Proceedings of the 40th Design Automation Conference (DAC '03), pp. 191–194, Anaheim, Calif, USA, 2003. View at Scopus
  12. L. Wei, Z. Chen, K. Roy, M. C. Johnson, Y. Ye, and V. K. De, “Design and optimization of dual-threshold circuits for low-voltage low-power applications,” IEEE Transactions on Very Large Scale Integration (VLSI) Systems, vol. 7, no. 1, pp. 16–24, 1999. View at Google Scholar
  13. L. Wei, Z. Chen, K. Roy, Y. Ye, and V. De, “Mixed-Vth (MVT) CMOS circuit design methodology for low power applications,” in Proceedings of the 36th Annual ACM/IEEE Design Automation Conference, pp. 430–435, New Orleans, La, USA, 1999.
  14. J. Jaffari and A. Afzali-Kusha, “New dual-threshold voltage assignment technique for low-power digital circuits,” in Proceedings of the 16th International Conference on Microelectronics (ICM '04), pp. 413–416, Tunis, Tunesia, 2004.
  15. P. Elakkumanan, K. Thyagarajan, K. Prasad, and R. Sridhar, “Optimal Vth assignment and buffer insertion for simultaneous leakage and glitch minimization though Integer Linear Programming (ILP),” in Proceedings of the 48th Midwest Symposium on Circuit and Systems (MWSCAS '05), vol. 2, pp. 1880–1883, 2005. View at Publisher · View at Google Scholar
  16. S. Gupta, J. Singh, and A. Roy, “A novel cell-based heuristic method for leakage reduction in multi-million gate VLSI designs,” in Proceedings of the 9th international Symposium on Quality Electronic Design (ISQED '08), pp. 526–530, San Jose, Calif, USA, 2008. View at Publisher · View at Google Scholar
  17. M. Guiney and E. Leavitt, “An introduction to openAccess: an open source data model and API for IC design,” in Proceedings of the 2006 Asia and South Pacific Design Automation Conference, pp. 434–436, Yokohama, Japan, 2006.