Task-Level Data Model for Hardware Synthesis Based on Concurrent Collections

Listing 19

TLDM specification of convergence algorithm.

tldm_data convergence_data(“convergence”);

tldm _iteration_domain id_ti;

id_ti.insert_iterator(iterator_t); // “t” for the while loop

id_ti.insert_iterator(iterator_i); // “i”

id_ti.insert_affine_constraint(“i”, 1, “>=”, 0); // i*1 >= 0

id_ti.insert_affine_constraint(“i”, -1, “N”, 1, “>”, 0); // -i+N > 0

id_ti.insert_affine_constraint(“t”, 1, “>=”, 0); // t >= 0

tldm_expression exe_condition(&iterator_t, “!”, &convergence_data);

id_ti.insert_exe_condition(&exe_condition);

// non-DSA access: different iterations access the same scalar data unit

tldm_access convergence_acc (&convergence_data, WRITE);

tldm_task task1(“task1”);

seq_cholesky.attach_id(&id_ti);

seq_cholesky.attach_access(&convergence_acc);

// dependence is needed to specify to avoid access conflicts

tldm_dependence dept(&task1, &task1);

// dependence : task1<t> → task1<t+1>

// dept.insert_affine_constraint (“t”, 1, 0, “->”, “t”, 1, 1); // (t+0) → (t+1)

// dependence are added to make the while loop iterations to execute in sequence, 0, 1, 2, …

< > :: [convergence]; 

[N] ->  < id_ti : t, j> {cond(!convergence); 0<=i<N;};

<id_ti> ::(task1) {body_id(“task1”)};

(task1: t, i) -> [convergence]

(task1 : t-1, 0..N) -> (task1 : t, 0..N);