Efficient Parallel Carrier Recovery for Ultrahigh Speed Coherent QAM Receivers with Application to Optical Channels

Abstract

This work presents a new efficient parallel carrier recovery architecture suitable for ultrahigh speed intradyne coherent optical receivers (e.g., ≥100 Gb/s) with quadrature amplitude modulation (QAM). The proposed scheme combines a novel low-latency parallel digital phase locked loop (DPLL) with a feedforward carrier phase recovery (CPR) algorithm. The new low-latency parallel DPLL is designed to compensate not only carrier frequency offset but also frequency fluctuations such as those induced by mechanical vibrations or power supply noise. Such carrier frequency fluctuations must be compensated since they lead to higher phase error variance in traditional feedforward CPR techniques, significantly degrading the receiver performance. In order to enable a parallel-processing implementation in multigigabit per second receivers, a new approximation to the DPLL computation is introduced. The proposed technique reduces the latency within the feedback loop of the DPLL introduced by parallel processing, while at the same time it provides a bandwidth and capture range close to those achieved by a serial DPLL. Simulation results demonstrate that the effects caused by frequency deviations can be eliminated with the proposed low latency parallel carrier recovery architecture.

1. Introduction

The recent emergence of the updated standards IEEE 802.3 for 40 and 100 gigabit per second (Gb/s) Ethernet and G.709 for 40 and 100 Gb/s optical transport network (OTN), as well as the first commercially available devices implementing these data rates, reveals the vertiginous growth on the bandwidth demand in the last decade [1, 2].

The projected increase on the bandwidth demand (e.g., ≥100 Gb/s) has set the bases for the next generation of Ethernet and OTN, and it has, therefore, renewed interest on coherent detection and spectrally efficient modulation techniques such as 𝑀-ary phase-shift keying (𝑀-PSK) and 𝑀-ary quadrature amplitude modulation (𝑀-QAM). More precisely, the conjunction among intradyne coherent detection, polarization-division multiplexing (PDM), 16-QAM, and electronic dispersion compensation (EDC) [3, 4] allows to reach good tradeoff among complexity, spectral efficiency, minimization of nonlinear distortions, and the possibility to completely compensate with zero penalty the main fiber channel impairments [3] (i.e., polarization mode dispersion (PMD) and chromatic dispersion (CD) [5]). In particular, intradyne detection is preferred over the alternative heterodyne or homodyne architectures because it replaces complex optical phase-locked loops (PLLs) with more robust and easier to implement digital carrier recovery (CR) techniques. In other words, all of these aspects can be summarized in an improved receiver sensitivity in comparison to intensity modulation direct detection (IM/DD) schemes [6, 7].

In this context, CPR fulfils a fundamental role in coherent optical receivers [3, 8]. Feedforward phase estimation schemes such as Viterbi-Viterbi (VV) [9] or blind phase search (BPS) [10] algorithms have been proposed for optical coherent receivers, because of their good laser linewidth tolerance and feasibility for parallel implementation. More specifically, significant amounts of CD lead to an enhancement of the phase noise introduced by the local oscillator and a lower tolerance with respect to carrier frequency offsets. In these feedforward CPR schemes, a perfect compensation of carrier frequency offset is assumed. However, this condition may not be always satisfied in practice. In fact, it has been shown that the phase error variance increases with the frequency offset, degrading the performance of the feedforward phase estimation stage [11]. Feedforward techniques to estimate and compensate frequency offset have been investigated in previous works [12–15]. Moreover, parallel architectures of these techniques are feasible for implementation in high-speed receivers. In particular, [15] has been conceived as data-aided (DA) algorithm that uses training sequences to enhance the capture range up to near 1/(2𝑇), being 𝑇 the symbol duration, whereas [12–14] are nondata-aided algorithm (NDA) with capture range close to 1/(8𝑇) for 16-QAM scheme.

Although accurate frequency offset estimation and compensation can be carried out by well-known techniques, a static frequency offset has been assumed in all these proposals. As it has been recently demonstrated, transmitter or local oscillator laser frequency instability caused by mechanical vibrations significantly degrades the performance of feedforward CPR algorithms [16]. Other effects such as power supply noise may also introduce laser frequency fluctuations which can be modeled as a frequency modulation with a sinusoid of large amplitude (e.g., ~250 MHz) and low frequency (e.g., ≤35 KHz) [16]. The effectiveness of frequency offset estimation techniques, such as those mentioned earlier, is limited due to the large amplitude of the modulation signal (i.e., large laser frequency change rate). Recent publications have proposed architectures for compensation of laser frequency fluctuations when quadrature phase-shift keying modulation (QPSK) is used [2, 17, 18]. For example, a two-stage carrier recovery parallel architecture based on a low-latency parallel DPLL and the feedforward VV CPR algorithm has been proposed in [17]. This technique offers an excellent tradeoff between complexity and performance for coherent QPSK receivers in the presence of laser phase noise, sinusoidal frequency jitter, and frequency offset. In this work, we generalize the technique introduced in [17] for application to 𝑀-QAM optical receivers.

As mentioned before, feedforward CPR blocks based on the VV or BPS algorithms achieve good laser linewidth tolerance and overcome some of the latency-related limitations [8]. We show here that traditional decision directed DPLLs [19] offer advantages in some aspects of the operation of CPR, for example, the tracking of large amplitude sinusoidal carrier frequency jitter experienced by typical lasers. A traditional PLL is often modeled as a linear filter, assumption which is useful to compute the small signal transfer function [19]. However, the PLL is actually a nonlinear filter precluding, in this way, the use of the unfolding techniques discussed by Parhi in [20], are applicable only to strictly linear filters. Therefore, a different approach to reduce the latency of the PLL parallel implementation must be found.

In the present work we introduce a new parallel carrier recovery algorithm which combines a novel low-latency parallel DPLL with a traditional feedforward CPR algorithm. The new low-latency parallel DPLL is used to compensate not only frequency offset but also frequency fluctuations. The proposed DPLL approach takes out of the feedback loop as much processing as possible in order to simplify the loop and reduce its latency. Then, the bottleneck of the critical PLL feedback path is broken by using a novel approximation to the DPLL computation, which provides a capture range and bandwidth close to those achieved by serial DPLLs [17, 21]. Computer simulations demonstrate that the degradations caused by frequency offset and laser frequency fluctuations can be eliminated with the proposed parallel carrier recovery technique. Unlike the superscalar parallelization (SP) methods [22–25], the technique proposed here does not require training symbols to avoid the acquisition problem. Moreover, the buffers required by the SP scheme are completely avoided in our approach.

The remainder of the paper is organized as follows. Section 2 presents the system model and analyzes the effects of the carrier frequency fluctuations on the receiver performance. Section 3 describes the two-stage carrier recovery technique. Section 4 introduces the new low-latency parallel DPLL, while numerical results are shown and discussed in Section 5. Finally, conclusions are drawn in Section 6.

2. System Model

Figure 1 shows a simplified block diagram of the coherent receiver with electronic dispersion compensation. Then, the sample at the equalizer output can be expressed as 𝑟_𝑛=𝑎_𝑛𝑒^𝑗𝛼𝑛+𝑧_𝑛, (1) where 𝑎_𝑛 is the 𝑛th transmitted symbol and 𝛼_𝑛 is the total phase noise. Component 𝑧_𝑛 represents the amplified spontaneous emission (ASE) noise sample, which is modeled as a white complex Gaussian random variable with power 𝜎² [3]. The equalized output signal (1) can be rewritten as 𝑟_𝑛=𝑟_𝑛𝑒^𝑗𝜃𝑛, (2) where |𝑟_𝑛| and 𝜃_𝑛 are the magnitude and the phase of the complex sample 𝑟_𝑛, respectively. In 𝑀-PSK and 𝑀-QAM systems, the symbol information is contained totally or partially in the phase of 𝑟_𝑛, respectively. The received phase 𝜃_𝑛 can be expressed as 𝜃_𝑛=𝜁_𝑛+Ω_𝑐𝑛+ΔΩ_𝑛+𝜙_𝑛, (3) where 𝜁_𝑛 is the phase of the transmitted symbol 𝑎_𝑛 and Ω_𝑐 is the angular carrier frequency offset given by Ω_𝑐=2𝜋𝑇𝑓_𝑐, with 𝑓_𝑐 and 𝑇 being the carrier frequency offset and the symbol duration, respectively. Term ΔΩ_𝑛 represents the phase change generated by frequency fluctuations. In this work we assume that the carrier is modulated by a sinusoidal interfering signal; therefore ΔΩ_𝑛=𝐴_𝑝Δ𝑓_𝑐sin2𝜋𝑇Δ𝑓_𝑐𝑛, (4) where 𝐴_𝑝 and Δ𝑓_𝑐 are the amplitude and frequency of the modulation tone.

Figure 1 

Simplified block diagram of the coherent receiver with equalization.

Component 𝜙_𝑛 is the total phase noise given by 𝜙_𝑛=𝜙^(laser)_𝑛+𝜙^(ASE)_𝑛, (5) where 𝜙^(laser)_𝑛 and 𝜙^(ASE)_𝑛 are the laser phase noise and the ASE generated phase noise, respectively. Laser phase noise is modeled as a Wiener process as follows: 𝜙^(laser)_𝑛=^𝑛_𝑘=−∞𝜂_𝑘, (6) where 𝜂_𝑘s are independent, identically distributed, Gaussian random variables with zero mean and variance 𝜎²_𝜂=2𝜋𝑇Δ𝜈, being Δ𝜈 the laser linewidth [8].

2.1. Feedforward CPR

Typical carrier recovery techniques for coherent optical receivers combine a frequency offset compensation stage followed by a feedforward phase estimation block based on the well-known VV or BPS algorithms (see Figure 2) [13]. Once the frequency offset is removed, the VV or BPS block estimate and compensate the phase noise.

Figure 2 

Simplified block diagram CPR based on BPS algorithm with frequency offset compensation.

Figure 3 shows a simplified block diagram of the VV algorithm implementation. The VV block estimates the phase noise based on the 𝑀th power of the received signal as follows: 𝜑_𝑛=1𝑀𝒰arg𝑢_𝑛, (7) where 𝒰 is the unwrap function and 𝑢_𝑛 is the output of the VV estimator given by 𝑢_𝑛=^𝑁−1_𝑖=0𝑟̃_𝑛−𝑖^𝑀, (8) with 𝑁 being an integer odd number which represents the VV estimator length (see [8] for more details).

Figure 3 

Block diagram of the Viterbi-Viterbi algorithm.

An alternative to the VV estimator is the so-called BPS algorithm shown in Figure 4. The BPS blocks estimates the phase noise as follows: 𝜑_𝑛𝜑=𝒰argmin_𝑏𝑔𝑟_𝑛̃,𝜑_𝑏, (9) where 𝜑_𝑏 is the test phase defined as 𝜑_𝑏=𝑏𝐵⋅𝜋2,𝑏∈{0,1,…,𝐵−1}, (10) where 𝐵 is the number of phases to be tested; term 𝑔(𝑟_𝑛̃,𝜑_𝑏) is given by 𝑔𝑟_𝑛̃,𝜑_𝑏=𝑠_𝑛,𝑏=^𝑁−1_𝑖=0𝑑_{𝑛−𝑖,𝑏}²=^𝑁−1_𝑖=0𝑟̃_𝑛−𝑖𝑒^−𝑗𝜑_𝑏−𝒬𝑟̃_𝑛−𝑖𝑒^−𝑗𝜑_𝑏², (11) where 𝒬(⋅) is the slicer function and 𝑁 is, again, the estimator length (see [10] for more details).

Figure 4 

Block diagram of the blind phase search algorithm.

Both VV and BPS techniques efficiently compensate the effects of the laser phase noise. Particularly, the VV architecture is preferred for 𝑀-PSK modulation schemes because of its uniform angular spacing and constant modulus between symbols. Although there exist alternatives that enable the VV to operate with 𝑀-QAM schemes [26], the BPS algorithm is preferred because it performs better in the presence of laser phase noise in spite of its greater computational complexity.

2.2. Effects of Frequency Fluctuations

Mechanical vibrations cause small deformations of electronic components, such as the laser cavity, leading to frequency fluctuations (see [16] and references therein). As expressed in the introduction, these fluctuations can be described as a frequency modulation with a sinusoidal signal of large amplitude (e.g., 𝐴_𝑝∼250 MHz) and low frequency (e.g., Δ𝑓_𝑐≤35 KHz). Without loss of generality, we consider in this work differential QPSK and 16-QAM differentially encoded in quadrant. Figures 5 and 6 show the optical signal-to-noise ratio (OSNR) penalty at a bit-error-rate (BER) of 10⁻³ versus the tone amplitude 𝐴_𝑝 for Δ𝑓_𝑐=35 KHz. We use the feedforward VV and BPS CPR schemes depicted in Figures 3 and 4, respectively, with 1/𝑇=32 giga-samples per second (Gs/s), laser linewidth Δ𝜈=250 KHz, and several values of the estimator length, 𝑁. Perfect estimation of the frequency offset is assumed. At the selected symbol rate, and within the jitter tone amplitude range of concern, QPSK does not show a significant penalty when the averaging block length is properly chosen. On the other hand, note that the performance in the 16-QAM case is significantly deteriorated with the amplitude of the frequency modulation tone, which agrees with that reported in [16]. Notice also that the value of the estimator length that minimizes the penalty depends on the tone amplitude. This fact suggests the need for an automatic adjustment algorithm for 𝑁.

Figure 5 

Performance of VV CPR with QPSK modulation versus the frequency deviation amplitude (𝐴𝑝) for Δ𝑓𝑐=35 KHz, 1/𝑇=32 Gs/s, and Δ𝜈=250 KHz.

Figure 6 

Performance of BPS CPR with 16-QAM versus the frequency deviation amplitude (𝐴𝑝) for Δ𝑓𝑐=35 KHz, 1/𝑇=32 Gs/s, Δ𝜈=250KHz, and 𝐵=32.

3. Carrier Recovery with Compensation of Frequency Fluctuations

Based on the results shown in Section 2.2, we conclude that the tracking of frequency fluctuations becomes an essential task in ultrahigh speed intradyne coherent optical receivers. Towards this end, a two-stage carrier recovery algorithm is proposed in this work (see Figure 7). A first CPR stage is based on a low-latency parallel DPLL, which is used to compensate not only frequency offset but also carrier frequency fluctuations. The second CPR stage is based on the renowned VV [9] or BPS [10] algorithm, which operates on the signal demodulated by the DPLL. The second CPR stage is mainly used to compensate the laser phase noise.

Figure 7 

Simplified block diagram of the two-stage carrier recovery technique.

Parallel architectures for both stages must be provided for multigigabit applications. Feedforward phase estimation schemes such as VV or BPS are attractive for high-speed coherent receivers owing to their good laser linewidth tolerance and feasibility for parallel implementation. Nevertheless, the low-latency parallel DPLL proposed in [17] has been designed for QPSK format. In the following section, we generalize the scheme introduced in [17] for application to 𝑀-QAM.

3.1. Phase Domain Digital PLL

We consider a phase domain DPLL in order to reduce computational complexity. The domain change results in the substitution of complex multipliers by real adders, allowing in this way to increase the processing rate of the system, a fundamental aspect in multigigabit communications where high processing rates are required.

In a decision directed carrier recovery loop (see Figure 8), the symbol information is first removed [19]. In QPSK receivers, this operation can be easily carried out in the phase domain as follows: 𝜙_𝑛=𝜃_𝑛𝜋/2, (12) where (⋅)_𝐻 denotes modulus 𝐻. In the absence of phase noise and frequency deviations (i.e., 𝜙_𝑛=0 for all 𝑛 and 𝑓_𝑐=Δ𝑓_𝑐=0), notice that 𝜙_𝑛=(𝜁_𝑛)_𝜋/2=𝜋/4 for all 𝑛. A similar approach can be adopted for 𝑀-QAM. For example, for 16-QAM the symbol phase 𝜁_𝑛 reduced to the first quadrant results in (𝜁_𝑛)_𝜋/2∈{arctan(1/3),𝜋/4,arctan(3)}. Figure 9 depicts the entire QPSK and 16-QAM constellations in the complex plane, where the labels 𝑖 and 𝑞 stand for the real and imaginary axes, respectively. Moreover, the shaded areas in Figure 9 highlight the quadrant reduction given by (12).

Figure 8 

Phase domain digital PLL.

(a)

(b)

Figure 9 

QPSK and 16-QAM square constellation.

The phase at the numerically controlled oscillator (NCO) output of a type II second-order DPLL (see Figure 8) can be expressed as 𝜓_𝑛=𝜓_𝑛−1+𝐾^(𝑝)𝜖_𝑛+𝐾^(𝑖)𝜖_𝑛−1, (13) where all addition operations in the following analysis are modulus 2𝜋, and the constants 𝐾^(𝑝) and 𝐾^(𝑖) are the loop proportional and integral gains, respectively; 𝜖_𝑛 is the phase error given by 𝜖_𝑛=𝜙_𝑛−𝜓_{𝑛−1𝜋/2}−𝜌_𝑛, (14) where 𝜌_𝑛 is the symbol phase of the transmit symbol reduced to the first quadrant; that is, 𝜌_𝑛=(𝜁_𝑛)_𝜋/2. Finally, term 𝜖_𝑛−1 in (13) is the accumulated phase error given by 𝜖_𝑛−1=^𝑛−1_𝑘=−∞𝜖_𝑘. (15)

Since the phase symbol is not known apriori at the receiver, we use a tentative decision of the transmit symbol to estimate the phase 𝜌_𝑛 as follows: 𝜌_𝑛≈𝑓𝑟_𝑛,𝜃_𝑛, (16) where 𝜃_𝑛 is the phase of the demodulated received sample, reduced to the first quadrant; that is, 𝜃_𝑛=𝜃_𝑛−𝜓_{𝑛−1𝜋/2}=𝜙_𝑛−𝜓_{𝑛−1𝜋/2}. (17)

Note that (𝑎+𝑏)_𝐻=((𝑎)_𝐻+(𝑏)_𝐻)_𝐻; therefore, since 𝜙_𝑛=(𝜃_𝑛)_𝜋/2, we can get (17). For example, for QPSK 𝜌_𝑛≈𝑓𝑟_𝑛,𝜃_𝑛=𝜋4∀𝑛, (18) while for 16-QAM, 𝜌_𝑛≈𝑓𝑟_𝑛,𝜃_𝑛=𝜋/4if𝑟_𝑛≥𝜌_𝑢or𝑟_𝑛≤𝜌_𝑙1arctan3if𝜌_𝑙<𝑟_𝑛<𝜌_𝑢and𝜃_𝑛≤𝜋4arctan(3)if𝜌_𝑙<𝑟_𝑛<𝜌_𝑢and𝜃_𝑛>𝜋4. (19)

Figure 10 shows the 16-QAM constellation reduced to the first quadrant of the complex plane and the decision boundaries according to (19).

Figure 10 

16-QAM square constellation after modulus 𝜋/2 operation.

3.2. Evaluation of DPLL for Tracking Frequency Fluctuations

The effectiveness of the decision directed DPLL to track frequency fluctuations is analyzed in the following section. In our carrier recovery scheme, the serial DPLL is used for compensation of frequency offset and fluctuations, while a feedforward CPR block based on the BPS algorithm is used for phase noise estimation. This carrier recovery architecture will be denoted as S-DPLL + BPS.

Figure 11 shows the OSNR penalty versus the modulation tone amplitude, 𝐴_𝑝, for Δ𝑓_𝑐=35 KHz and Δ𝜈=250 KHz. The BPS filter length is 𝑁=21, while the test phase number is 𝐵=32. Note that the performance degradation caused by the carrier frequency fluctuation is eliminated with the new combined S-DPLL + BPS carrier recovery technique.

Figure 11 

Performance of the proposed S-DPLL + BPS carrier recovery scheme versus the frequency deviation amplitude (𝐴𝑝) for Δ𝑓𝑐=35 KHz, 1/𝑇=32 Gs/s, Δ𝜈=250 KHz, 𝑁=21, and 𝐵=32.

Figure 12 presents the tolerance of BPS and S-DPLL + BPS architectures to the laser phase noise in the presence of a frequency modulation tone with 𝐴_𝑝=140 MHz, Δ𝑓_𝑐=35 KHz. These models were compared with the BPS algorithm without influence of frequency fluctuations (i.e., 𝐴_𝑝=0). The last mentioned scheme is used as a benchmark. It is interesting to highlight the important degradation caused by the frequency fluctuations in the solution solely based on the BPS algorithm. Again notice that the effects of the carrier frequency fluctuations are mitigated by using the proposed S-DPLL + BPS carrier recovery algorithm.

Figure 12 

Laser linewidth tolerance in the presence of vibration-induced frequency fluctuations for Δ𝑓𝑐=35 KHz, 𝐴𝑝=140 MHz, 1/𝑇=32 Gs/s, 𝑁=21, and 𝐵=32.

4. New Low Latency Parallel DPLL for M-QAM

Maximum clock frequency of complex digital signal processors for the state of the art 28 nm CMOS technology is limited to less than 1 GHz. Thus, the use of parallel processing techniques for the implementation of multigabits per second receivers is mandatory. Unfortunately, the nonlinear filter nature of the DPLL impedes the use of the unfolding techniques [20]. Since low latency is a key factor to track frequency fluctuations, then we develop a new approach to reduce the latency in the parallel implementation of DPLL.

4.1. Parallel Type II DPLL for M-QAM

From (13) it is possible to show that 𝜓_𝑛+1=𝜓_𝑛+𝐾^(𝑝)𝜖_𝑛+1+𝐾^(𝑖)𝜖_𝑛=𝜓_𝑛−1+𝐾^(𝑝)𝜖_𝑛+𝜖_𝑛+1+𝐾^(𝑖)𝜖_𝑛−1+𝜖_𝑛, (20) where 𝜖_𝑛+1=𝜙_𝑛+1−𝜓_𝑛𝜋/2=𝜙_𝑛+1−𝜓_𝑛−1−𝐾^(𝑝)𝜖_𝑛−𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝜌_𝑛+1 (21) with 𝜌_𝑛+1 given by (16) and 𝜃_𝑛+1=𝜙_𝑛+1−𝜓_𝑛−1−𝐾^(𝑝)𝜖_𝑛−𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}. (22)

For the type II second-order DPLL, the steady-state error is zero (i.e., lim_𝑛→∞𝜖_𝑛→0) [19]. Thus, assuming that the bandwidth of the loop is low-to-moderate such 𝐾^(𝑝)≪1, the contribution of the term 𝐾^(𝑝)𝜖_𝑛 can be neglected; therefore the phase error (21) results in 𝜖_𝑛+1≈𝜙_𝑛+1−𝜓_𝑛−1−𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝜌_𝑛+1, (23) where 𝜌_𝑛+1 is given by 𝜌_𝑛+1=𝑓𝑟_𝑛+1,𝜃_𝑛+1 (24) with 𝜃_𝑛+1=𝜙_𝑛+1−𝜓_𝑛−1−𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}. (25) Furthermore, since the accumulated phase error varies slowly with time (i.e., 𝜖_𝑛≈𝜖_𝑛−1), from (20) and (23), we can obtain 𝜓_𝑛+1≈𝜓_𝑛−1+𝐾^1(𝑝)_𝑘=0𝜙_𝑛+𝑘−𝜓_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝐾^1(𝑝)_𝑘=0𝜌_𝑛+𝑘+2𝐾^(𝑖)𝜖_𝑛−1, (26) where 𝜌_𝑛+𝑘 is given by 𝜌_𝑛+𝑘=𝑓𝑟_𝑛+𝑘,𝜃_𝑛+𝑘 (27) with 𝜃_𝑛+𝑘=𝜙_𝑛+𝑘−𝜓_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}. (28)

Let 𝑃 be the parallelization factor. Following a similar analysis, it is possible to derive that 𝜓_𝑛+𝑚≈𝜓_𝑛−1+𝐾^𝑚(𝑝)_𝑘=0𝜙_𝑛+𝑘−𝜓_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝐾^𝑚(𝑝)_𝑘=0𝜌_𝑛+𝑘+(𝑚+1)𝐾^(𝑖)𝜖_𝑛−1,𝑚=0,1,…,𝑃−1. (29)

A type II DPLL can be considered as two separate feedback loops: the proportional and integral loops (see Figure 13). Thus, the NCO output (29) can be rewritten as 𝜓_𝑛+𝑚=𝜓^(𝑝)_𝑛+𝑚+𝜓^(𝑖)_𝑛+𝑚,𝑚=0,1,…,𝑃−1, (30) where 𝜓^(𝑝)_𝑛+𝑚 and 𝜓^(𝑖)_𝑛+𝑚 are the NCO components due to the proportional and integral paths, respectively.

Figure 13 

Modified phase domain digital PLL.

4.2. Proportional Loop

From (29), it is simple to show that 𝜓^(𝑝)_𝑛+𝑚≈𝜓^(𝑝)_𝑛−1+𝐾^𝑚(𝑝)_𝑘=0𝜙_𝑛+𝑘−𝜓_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝐾^𝑚(𝑝)_𝑘=0𝜌_𝑛+𝑘. (31)

From (12) and (17), note that 𝜙_𝑛+𝑘−𝜓_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}=𝜙_𝑛+𝑘−𝜓^(𝑖)_𝑛−1−𝜓^(𝑝)_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}=𝜃_𝑛+𝑘−𝜓^(𝑖)_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}−𝜓^(𝑝)_{𝑛−1𝜋/2}. (32)

Thus, expression (31) can be rewritten as 𝜓^(𝑝)_𝑛+𝑚≈𝜓^(𝑝)_𝑛−1+𝐾^𝑚(𝑝)_𝑘=0𝜙_𝑛+𝑘−𝜓^(𝑝)_{𝑛−1𝜋/2}−𝐾^𝑚(𝑝)_𝑘=0𝜌_𝑛+𝑘, (33) where 𝜙_𝑛+𝑘=𝜃_𝑛+𝑘−𝜓^(𝑖)_𝑛−1−𝑘𝐾^(𝑖)𝜖_{𝑛−1𝜋/2}. (34)

From (32) and (34), note that (28) can be rewritten as 𝜃_𝑛+𝑘=𝜙_𝑛+𝑘−𝜓^(𝑝)_{𝑛−1𝜋/2}. (35)

For example, from (18) and (33) the NCO output (33) for QPSK reduces to [17] 𝜓^(𝑝)_𝑛+𝑚≈𝜓^(𝑝)_𝑛−1+𝐾^𝑚(𝑝)_𝑘=0𝜙_𝑛+𝑘−𝜓^(𝑝)_{𝑛−1𝜋/2}−𝐾^(𝑝)()𝜋𝑚+14. (36)

Unfortunately, it is still highly complex for 𝑀-QAM (33) to be implemented with digital signal processors for the state of the art 28 nm CMOS technology as a result of the complexity required to carry out in one clock cycle the computation of the function 𝜌_𝑛+𝑘=𝑓(|𝑟_𝑛+𝑘|,𝜃_𝑛+𝑘) and then the last summation in (33). This problem can be mitigated if terms 𝑓(|𝑟_𝑛+𝑘|,𝜃_𝑛+𝑘) are precomputed by using the NCO output of the previous clock cycle; that is, 𝜃_𝑛+𝑘≈𝜙_𝑛+𝑘−𝜓^(𝑝)_{𝑛−1−𝑃𝜋/2}. (37)

As we shall show later, the performance degradation caused by (37) is negligible in practical situations (e.g., 16-QAM with 𝑃≤80). For 16-QAM, this behavior can be understood from the facts that (i) only the nondiagonal symbols use 𝜃_𝑛+𝑘 (see (19)) and (ii) laser frequency fluctuations are slow compared to the baud rate.

A low-latency parallel implementation of the proportional loop can be easily derived from (33)–(37). Figure 14 shows the architecture of the low-latency parallel type I DPLL. Block “𝐹_𝑘” (𝑘=0,1,…,𝑃−1) computes terms 𝜌_𝑛+𝑘=𝑓(|𝑟_𝑛+𝑘|,𝜃_𝑛+𝑘) with 𝜃_𝑛+𝑘 given by (37), while block “𝑊_𝑘” evaluates the summations of (33). Block “𝑊_𝑘” (𝑘=0,1,…,𝑃−1) uses a fast adder (e.g., a Wallace tree and carry save adder [20]) to quickly calculate the NCO output (33). Furthermore, the gain 𝐾^(𝑝) is assumed to be a power of 2 (i.e., 𝐾^(𝑝)=2^−𝑁𝑝 with 𝑁_𝑝 being a positive integer). In this way, multiplications by the proportional gain 𝐾^(𝑝) are reduced to simple bit shift operations. Again note that all additions in (33) are modulus 2𝜋.

Figure 14 

Implementation of the low latency parallel proportional loop for 𝑀-QAM.

4.3. Integral Loop

On the other hand, from (29) and Figure 13, we can also derive the NCO component due to the integral path as follows: 𝜓^(𝑖)_𝑛+𝑚≈𝜓^(𝑖)_𝑛−1+(𝑚+1)𝐾^(𝑖)𝜖_𝑛−1. (38)

The accumulated phase error can be expressed as 𝜖_𝑛+𝑚=^𝑛+𝑚_𝑘=−∞𝜖̂_𝑘=𝜖_𝑛−1+^𝑛+𝑚_𝑘=𝑛𝜖̂_𝑘. (39)

Based on (12), (14), (30), (34), and (38), the accumulated phase error can be evaluated as 𝜖̂_𝑘=𝜙_𝑘−𝜓^(𝑝)_𝑘−1−𝜓^(𝑖)_{𝑘−1𝜋/2}−𝜌_𝑘=𝜙_𝑘−𝜓^(𝑝)_{𝑘−1𝜋/2}−𝜌_𝑘. (40)

4.4. Parallel Architecture of the New DPLL

A parallel implementation of the type II DPLL can be easily achieved as depicted in Figure 15. Term 𝐿=𝑙𝑃 with 𝑙 being a positive integer represents the latency required to compute all the operations of the integral path (e.g., the phase error computation (PEC) defined in (40)). Since the latency in this path is not as critical as in the proportional loop, its effect on the DPLL performance will be negligible, as we will show in the next section. Similarly to 𝐾^(𝑝), the integral gain 𝐾^(𝑖) is assumed to be a power of 2 (i.e., 𝐾^(𝑖)=2^−𝑁𝑖 with 𝑁_𝑖 being a positive integer).

Figure 15 

Implementation of the low latency parallel type II DPLL.

Figure 16(a) shows a possible implementation of the block “𝑊_𝑃−1”, and Figure 16(b) depicts an example of a tentative implementation of the “𝐹_𝑘” block based on look-up tables for 16-QAM.

(a)

(b)

Figure 16 

Block diagram of the implementation of (a) “𝑊𝑃−1” module and (b) block “𝐹𝑘” for 16-QAM.

5. Numerical Results

In this section we evaluate the effectiveness of the proposed two-stage CPR. We use 16-QAM differentially encoded in quadrant on a nondispersive noisy channel with 1/𝑇=32 Gs/s. The OSNR at a given bit-error-rate (i.e., BER of 10⁻³) is also used as a measure of the efficiency of the proposed CR loop. Two different type II DPLLs were simulated for comparison purposes: the already mentioned serial DPLL (S-DPLL) and the proposed low-latency parallel DPLL (P-DPLL) shown in Figure 15 with different parallelization factors. Moreover, the BPS algorithm with filter length 𝑁=21 and 𝐵=32 test phase values was considered.

The frequency responses of the DPLLs are depicted in Figure 17. The loop filter gains were selected in order to obtain maximum bandwidth with 0.5 dB maximum peaking (see Table 1). For the optical system considered here, these values of bandwidth and peaking provide a good tradeoff between capture range and the residual phase noise power at the input of the slicer (see Figure 1).

Table 1 

DPLL Parameters.

Figure 17 

Frequency response of the serial and low-latency parallel DPLL.

Due to the fact that frequency offset values in intradyne receivers exceed the maximum theoretical limit of 1/(8𝑇) [27] that can be reached by decision directed algorithms at the considered symbol rate (i.e., ±5 GHz; see [28]), typical intradyne coherent optical receivers are provided with a coarse carrier frequency recovery (CCFR) stage [2] that minimizes or reduces to zero this frequency gap to values in the theoretical range. However, residual frequency offset after CCFR can surpass the tolerance of CPR algorithms like the VV and the one considered in this work, that is, BPS. The capture range for the proposed P-DPLL is ~±4 GHz, which is close to the maximum theoretical frequency offset value for the given symbol rate (i.e., 1/(8𝑇)=4 GHz). Gear shifting is applied into the proportional and integral gains during the capture period.

Figure 18(a) shows the BPS CPR tolerance to the joint effect of the laser phase noise and the sinusoidal frequency tone amplitude, 𝐴_𝑝. At the same time Figure 18(b) depicts the performance of the combined architecture P-DPLL + BPS with 𝑃=64 under the same conditions as the ones already mentioned. It is interesting to note in Figure 18(b) the significant improvement in terms of sinusoidal frequency tolerance of the combined architectures in relation to the single stage CPR solely based on BPS. In other words, this improvement is evidenced in the increase of the contour line slope, getting parallel (i.e., independent) to the 𝐴_𝑝 axis.

(a)

(b)

Figure 18 

Surface of performance of the treated CPR algorithms under the joint effect of laser phase noise and frequency fluctuation. (a) BPS and (b) P-DPLL + BPS schemes with Δ𝑓𝑐=35 kHz, 1/𝑇=32 Gs/s, 𝑃=64, 𝑁=21, and 𝐵=32.

Figure 19 complement the current study for several values of the parallelization factor under the same conditions earlier detailed. Particularly, Figure 19 shows the performance of the two stage CPR architecture DPLL in conjunction with BPS algorithm using 16-QAM scheme. From the present study it is possible to derive Figure 20 where the efficiency of the proposed approximation for the parallelization of the DPLL is evidenced. Even though the 16-QAM format seems to be sensible to the effect of the parallelization factor, it is possible to highlight that the performance remains constant in a wide range of the parallelization axis and solely increases the penalization for large values of laser linewidth (i.e., Δ𝜈𝑇).

(a)

(b)

(c)

(d)

Figure 19 

Surface of performance of the P-DPLL + BPS architecture under the joint effect of laser phase noise and frequency fluctuation for several parallelization factors with Δ𝑓𝑐=35 kHz, 1/𝑇=32 Gs/s, 𝑁=21, and 𝐵=32.

(a)

(b)

Figure 20 

Two-stage CPR performance versus the parallelization factor. P-DPLL + BPS with Δ𝑓𝑐=35 kHz, 1/𝑇=32 Gs/s, 𝑁=21, and 𝐵=32 using 16-QAM scheme.

5.1. Impact of Decision Errors

The impact of the decision errors in terms of the variance of the estimated phase is analyzed for two different PLLs with the same bandwidth against the modified Cramer-Rao bound (MCRB) [29]. The Cramer-Rao lower bound (CRLB) can be considered as a fundamental limit on the performance that a linearized system can reach in the absence of decision errors [30]. In other words, the optimum theoretical bound is achieved under the simplifying assumption that the additive noise does not affect the receiver decisions about the data symbols. Simulation results for (i) the serial DPLL (S-DPLL) and (ii) the parallel DPLL (P-DPLL) with a parallelization factor of 𝑃=80 are shown in Figure 21(a).

(a)

(b)

Figure 21 

(a) Decision errors impact on the P-DPLL performance against the modified Cramer-Rao lower bound, 1/𝑇=32 Gs/s, using 16-QAM scheme. (b) Bit-error-rate of the DPLLs under analysis.

At the OSNR regime of interest in the application considered in our work (i.e., PDM-16-QAM, 1/𝑇=32 Gs/s, BER<10⁻²→OSNR>18 dB), it can be observed that the phase noise variance in the proposed parallel DPLL is sliglthy higher than that experienced in a serial DPLL. Nevertheless, notice that the impact of this phase variance increase on the performance in terms of bit-error-rate (BER) is practically negligible (see Figure 21(b)). Finally, it is important to highlight that catastrophic errors caused by cycle slips are avoided in the proposed carrier recovery architecture by using differential 16-QAM [11].

6. Conclusion

A new DPLL-based carrier recovery architecture for high speed optical coherent receivers has been introduced in this paper. The proposed parallel scheme builds upon a novel DPLL computation, which breaks the bottleneck of the feedback path. We have shown here a novel approach that leads to a simple parallel implementation. Furthermore, it has also been demonstrated that the new parallel DPLL can provide a bandwidth and capture range similar to those achieved by the serial DPLL.

The proposed two-stage carrier recovery architecture based on a low-latency parallel DPLL and a feedforward phase estimator BPS offers a low complexity, high performance, integral solution to the frequency, and phase compensation in coherent optical systems. This solution outperforms previously proposed architectures when all optical channel impairments present in real applications, including laser phase noise, sinusoidal frequency jitter, and frequency offset, are accounted for in the modeling.

Acknowledgment

This paper has been supported in part by the ANPCyT (PICT2011-2527), MINCyT, Fundación Tarpuy, and Fundación Fulgor.