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Journal of Electrical and Computer Engineering
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2013
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Article
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Tab 13
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Research Article
Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs
Table 13
Comparison between different scenarios for 3 : 2 asymmetric FinFET compressor.
Scenario
(pA)
(ps)
Static power * delay (yJ)
Number of transistors
1
10.62
31.47
401
30
2
19.92
31
741
22
3
17.25
24.56
508
18