Research Article

Ultra-Low Leakage Arithmetic Circuits Using Symmetric and Asymmetric FinFETs

Table 5

Results for the carry circuit.

IG/LP modeSymmetric = −0.2 V[4] Symmetric = −0.2 VAsymmetric = 0 V

(pA)16.4222.102.81
(ps)11.9423.8813.63
Static power * delay (yJ)235.26633.3045.96