Journal of Electrical and Computer Engineering / 2013 / Article / Tab 4

Research Article

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Table 4

Synthesis results for parallel DFFE architecture for -PAM and with 28 nm CMOS technology.

 (MHz) Number of cells Number of components


The total number of cells and components normalized to the values of and .

We are committed to sharing findings related to COVID-19 as quickly and safely as possible. Any author submitting a COVID-19 paper should notify us at help@hindawi.com to ensure their research is fast-tracked and made available on a preprint server as soon as possible. We will be providing unlimited waivers of publication charges for accepted articles related to COVID-19.