Journal of Electrical and Computer Engineering / 2013 / Article / Tab 4

Research Article

A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Table 4

Synthesis results for parallel DFFE architecture for -PAM and with 28 nm CMOS technology.

 (MHz) Number of cells Number of components

The total number of cells and components normalized to the values of and .

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