A Low-Complexity Decision Feedforward Equalizer Architecture for High-Speed Receivers on Highly Dispersive Channels

Table 4

Synthesis results for parallel DFFE architecture for 2-PAM and 𝑅=𝐿+1 with 28 nm CMOS technology.

𝑓clock (MHz)	𝑃	𝐿	Number of cells^†	Number of components^†
625.0	16	5	1.00	1.00
625.0	16	10	5.19	4.18
312.5	32	5	1.96	2.00
312.5	32	10	10.03	9.62
312.5	32	30	180.65	159.00

†The total number of cells and components normalized to the values of 𝑃=16 and 𝐿=5.