An FPGA-Integrated Time-to-Digital Converter Based on a Ring Oscillator for Programmable Delay Line Resolution Measurement

Table 3

Brief comparison with previous works.

	[6]	[7]	[8]	[12]	This work
Structure	Cyclic	True pipeline	SAR-ADC	Vernier	Ring oscillator
Process (nm)	130	65	65	65	65
Device	ASIC	ASIC	ASIC	FPGA	FPGA
DNL (LSB)	±0.7	0.6	−0.7/1.0	N/A	N/A
INL (LSB)	−3~+1	1.7	−2.7/1.7	−0.93~0.75	N/A
Resolution (ps)	1.25	1.12	0.84	1.58	Equivalent to 0.4