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Journal of Electrical and Computer Engineering
/
2014
/
Article
/
Tab 2
/
Research Article
A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique
Table 2
The zero bias threshold voltages of transistors.
Transistors
NMOS
PMOS
Low-
High-
Low-
High-
(V)
0.471
0.853
ā0.423
ā0.771