A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique

<table class="table-group" id="tab6"><tr><td><table class="table"><tr><td class="thead-hr" colspan="6"><hr/></td></tr><tr class="thead"><td align="left">Flip-flops</td><td align="center">ST-TG-FF</td><td align="center">Mutoh-FF</td><td align="center">Balloon-FF</td><td align="center">Memory-TG-FF</td><td align="center">ADR-FF</td></tr><tr><td class="thead-hr" colspan="6"><hr/></td></tr><tr><td align="left">Area (um<sup>2</sup>)</td><td align="center">2.63</td><td align="center">14.29</td><td align="center">10.27</td><td align="center">9.68</td><td align="center">9.22</td></tr><tr class="table-tr"><td colspan="6"><hr class="tbody-hr"/></td></tr></table></td></tr></table>

Journal of Electrical and Computer Engineering

tab6

Table 6

Table 6: A Low Leakage Autonomous Data Retention Flip-Flop with Power Gating Technique 