New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources

Table 3

Delay parameter of the proposed designs versus the output load(s).

Designs	Without any output loads		With the output load transistor		With the output load transistor and 4 copies of the output current
	Delay (psec) TMin	Delay (psec) TMax	Delay (psec) TMin	Delay (psec) TMax	Delay (psec) TMin	Delay (psec) TMax
CSTMin1	14.23	—	14.44	—	14.40	—
CSTMin2	11.17	—	13.45	—	13.34	—
CSTMax1	—	13.60	—	13.79	—	13.80
CSTMax2	—	13.71	—	14.03	—	13.99
CITMin/Max1	18.48	20.68	18.81	21.31	18.76	21.20
CITMin/Max2	18.11	21.38	18.46	21.72	18.53	22.08
CITMin/Max3	17.57	18.82	17.76	19.27	17.71	19.33