Journal of Electrical and Computer Engineering / 2015 / Article / Tab 3

Research Article

New Current-Mode Integrated Ternary Min/Max Circuits without Constant Independent Current Sources

Table 3

Delay parameter of the proposed designs versus the output load(s).

DesignsWithout any output loads With the output load transistor With the output load transistor and 4 copies of the output current
Delay (psec) TMinDelay (psec) TMaxDelay (psec) TMinDelay (psec) TMaxDelay (psec) TMinDelay (psec) TMax

CSTMin114.2314.4414.40
CSTMin211.1713.4513.34
CSTMax113.6013.7913.80
CSTMax213.7114.0313.99
CITMin/Max118.4820.6818.8121.3118.7621.20
CITMin/Max218.1121.3818.4621.7218.5322.08
CITMin/Max317.5718.8217.7619.2717.7119.33

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