Journal of Electrical and Computer Engineering / 2015 / Article / Fig 4

Research Article

Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Figure 4

Routing deadlock in unidirectional torus (a) and unidirectional mesh (b), deadlock recovery diagram (c).
(a) Unidirectional torus
(b) Unidirectional mesh
(c) Deadlock recovery

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