Applying Partial Power-Gating to Direction-Sliced Network-on-Chip

Table 1

Network configuration and workload.

Topology	8 × 8 mesh and torus
Router parameter (for each design)	Virtual channel flow control, 3-stage pipeline, 128-bit channel, 4 VCs/channel, and 4 buffer entries/VC
Synthetic traffic	Single flit per packet and Poisson distribution injection
SPLASH trace	Single flit per control packet and 5 flits per data packet