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Journal of Electrical and Computer Engineering
Volume 2015, Article ID 905718, 11 pages
Research Article

Drive Current Enhancement in TFET by Dual Source Region

School of Microelectronics, Xidian University, Xi’an 710071, China

Received 9 January 2015; Revised 15 April 2015; Accepted 3 May 2015

Academic Editor: Muhammad Taher Abuelma’atti

Copyright © 2015 Zhi Jiang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper presents tunneling field-effect transistor (TFET) with dual source regions. It explores the physics of drive current enhancement. The novel approach of dual source provides an effective technique for enhancing the drive current. It is found that this structure can offer four tunneling junctions by increasing a source region. Meanwhile, the dual source structure does not influence the excellent features of threshold slope (SS) of TFET. The number of the electrons and holes would be doubled by going through the tunneling junctions on the original basis. The overlap length of gate-source is also studied. The dependence of gate-drain capacitance and gate-source capacitance on gate-to-source voltage and drain-to-source voltage was further investigated. There are simulation setups and methodology used for the dual source TFET (DS-TFET) assessment, including delay time, total energy per operation, and energy-delay product. It is confirmed that the proposed TFET has strong potentials for VLSI.

1. Introduction

Consumer electronics meet minimizes active and leakage power by scaling down the supply voltage below 0.5 V [1]. The proposed TFET has been the subject of intense investigation in the last decade. It has gained an immense popularity because of its lower threshold slope and off-state current [24]. Always operated in highly reversed conditions of p-n junctions, TFETs also present significant low power dissipation. The conduction current in TFETs is essentially generated by the band-to-band tunneling (BTBT) of carriers through the forbidden-band gap, and the tunnel probability is mainly governed by the applied voltage, and TFETs devices produce an ideal on-off switching with a steep threshold slope [58]. However, experimental results show that the on-state currents are typically much smaller than those provided by metal-oxide-semiconductor field-effect transistor (MOSFET).

The main challenge for those boosters is to improve its on-state current without degrading the device performance. In order to address these issues, a low on-state current has been reported to dramatically improve with the use of high- gate dielectric, silicon on insulator technology [46], and double-gate (DG) architecture [7]. Further developments are necessary in issues such as the formation of the high- gate stack with low interface state density and low gate leakage current [8]. The double gate (DG) can have a better gate control over the channel. In addition, many methods have been proposed, such as heterojunctions [9, 10] and III–V materials [1116], in which the tunneling probability is enhanced by the reduction of tunneling width with the conduction or valence band discontinuities. However, the ambipolar leakage current was also increased; poor SS have been seen in them.

Although numerous advanced techniques have been proposed to more effectively control the tunnel width for improving on-state current and lowing the threshold slope (SS) in TFET, most of these methods are negative effect; what is more, the drawback of the TFET is obviously reflected; and the ambipolar leakage current were also increased simultaneously. Fortunately, TFETs have been experimentally demonstrated in a new structure that causes the gate field to be easy to penetrate the channel region.

The structures of the above TFETs are generally design by adopting only one source, drain, and one channel region. These structures enhance the tunneling ability; however, the tunneling areas were not made larger. TFET is a gated p-i-n diode; it exploits a BTBT mechanism of electrons from the valance band of the source to the conduction band of the channel region to generate current [2]. In terms of a DG TFET, if there were two source regions, the two source regions share the drain region; there will be a 50% increase in the total number of electrons and holes.

The key idea of present work is that common drain and two source regions were used. If the double gate and dual source TFET (DS-TFET) were recruited, four tunneling junctions will exist in the new geometry, which results in the increasing in the total number of electrons and holes in those tunnel junctions without influencing the threshold slope. This paper will show the dual source structure, realized in Ge/Si heterojunction TFET. This gate-source all-overlap structure geometry can also lead to the increase of the on-state current . In addition, longer length of drain region could suppress the ambipolar leakage current .

2. Device Structure and Simulation

This DS-TFET device can be fabricated using the process flow shown in Figure 1(a): first, drain region is in the middle of the device by wet chemical etching process; drain doping region is then formed by ion implantation. Two source regions end in the device, which is formed by chemical etching and formed by ion implantation. Then the wet chemical etching method etches the layer, which is replaced by the through the chemical vapor deposition (CVD). Then the drain and source electrode is formed by CVD. At last, spacers are formed and gate contact is defined. The device structure for dual source tunnel field-effect transistor (n-type TFET) used in this paper is shown in Figure 1(b). The parameters for the dual source structure in this simulation are the highly boron-doped p-region ( cm−3), the lightly phosphorous-doped n-region ( cm−3), and the highly phosphorous-doped n-region ( cm−3) to reduce ambipolar effects act as the source, the channel, and the drain, respectively. For simplicity of explanation, Ge/Si heterojunction TFET in this work with body thickness () of 10 nm, electrical oxide thickness of 2 nm, and channel length is 45 nm. The gate work function () was designed to be 4.6 eV.

Figure 1: (a) Process flow of DS-TFET. (i) Wet chemical etching of oxide layer. (ii) Drain implantation. (iii) Wet chemical etching of oxide layer. (iv) Source implantation. (v) Wet chemical etching and CVD for metal electrode. (v) Spacer formation and gate electrode. (b) Two-dimensional cross section of the simulated device structure for DS-TFET and conventional TFET:  nm,  nm,  nm,  nm,  nm, and  nm.

For the device operation of an n-TFET, a positive is applied. The mechanism of current flow in this device is based on the BTBT of electrons from the valance band of source region that is below the bottom of the conduction band of the channel region. The tunneling of electron takes place on the edges of the gate near the source. Silicon is an indirect band gap material, so indirect lateral tunneling dominates the main part of the total current in those conventional TFETs. Due to the corresponding smaller BTBT generation rate, the on-state current is very small. When the gate overlaps the source completely, the indirect current will be enlarged with the increasing overlap areas, the final tunneling current is also obviously increased in the uniform field limit. Another reason is that two source regions, the total tunneling electrons, are twice as large as a single p-i-n structure TFET.

In order to reduce the ambipolar current, longer length drain region is used in this structure. Now, here exists an intrinsic drift region, and the gate could not influence the channel-drain tunneling junction; hence, the ambipolar and leakage current could be suppressed.

Drain current was studied through TCAD simulator, employing dynamic nonlocal tunneling models, and the standard drift-diffusion carrier transport and Shockley-Read-Hall (SRH) recombination models and Lombardi’s mobility model. Although the use of a classical drift-diffusion model or an abrupt doping profile, this does not have much impact on the focus of this paper and relative results due to variation in different device parameters.

3. Results and Discussion

3.1. Current-Voltage Characteristics

Figure 2(a) shows the transfer characteristics of the new structure DS n-TFET and conventional n-TFET with the drain-to-source voltage at  V. Threshold voltage is the value of when is a constant current of and the value of is about 0.52 V, which is shown in Figure 2(a). All other device parameters for the two devices remained the same, and the high- gate dielectrics oxide thickness is 2 nm. In the first case, the new device is a structure without considering gate-channel underlap and overlap situations. An on-state current of 0.93 μA/μm and an on/off ratio of are obtained with a of 1.0 V in the DS-TFET; the on-state current of DS-TFET is nearly twice than that of conventional TFET. This result indicates that the dual source regions contribute to the tunneling current.

Figure 2: Device characteristics for the new structure n-TFET with 10-nm-thick silicon body and conventional n-TFET: (a) logarithmic and linear transfer characteristics for different values of ; (b) simulated output characteristics at different values of the gate overdrive .

Output characteristics for different values of the gate overdrive voltage for the DS-TFETs are shown in Figure 2(b). For different gate overdrive voltages . It is observed that initially very rapidly increases with increasing . As shown, the drain current saturates for drain voltages above approximately 1.2 V. Finally, an increase in results in sustained growth in channel potential; some of the electrons are pulled back to common drain, so the electron concentration will reduce in the channel, a good saturation of , at higher . There is a perfect saturation of the drain current in Figure 2(b). The pinch off voltage is found to be ~1.1 V in Figure 2(b) for overdrive voltage  V. It is evident in Figure 2(a) that does not increase for further increase in beyond the pinch off value of ~1.1 V.

The excellent characteristics of the DS-TFET can be obtained by using heterojunction. A Si-based heterojunction can be used to reduce the effective tunneling barrier height by replacing the Si in source region with Ge (all the dimension for simulated devices are same, gate length is 45 nm and oxide thickness is 2 nm). The on-state current of the Ge/Si heterojunction for HDS-TFET can reach 10 μA/μm at  V, as shown in Figure 3(a).

Figure 3: (a) Transfer characteristics of the Ge/Si DS-TFET, DS-TFET, and conventional TFET; (b) ratio versus gate length.

The ratio for the conventional TFET, DS-TFET, and Ge/Si DS-TFET is shown in Figure 3(b). The DS-TFET has better ratio than that of conventional TFET. All other dimensions and parameters for all the devices in this case are kept the same. At smaller gate lengths, the SRH current is dominant of total current. However, the short channel effect affects the SRH current which leads to the increasing of the off-current and the smallest ratio at 10 nm gate length. When exceeds 35 nm, the BTBT current cannot be increased and off-current will be unaffected. Hence the ratio remains the same.

Extract the threshold voltage swing, for a given gate voltage . The threshold voltage slope (SS) is defined as

It is worth noting that the threshold slope of the HDS-TFET is only half of the DS-TFET. As can be also seen in Figure 3, the simulated on-state current is about three orders of magnitude compared to the DS-TFET and conventional TFET, and the on/off ratio is also about .

3.2. Analysis of Gate-To-Source Capacitance and Gate-To-Drain Capacitance

Figure 4 shows the small signal total gate (), gate-to-source (), and gate-to-drain () of the conventional n-type TFET and n-type DS-TFET. and are extracted from the small-signal AC simulations at a frequency of 1 MHz. In terms of the MOSFET, the total gate capacitance is known to be equally distributed between the source and drain terminals. However, when the DS-TFET is forward biased, the terminal bias makes the entire gate capacitance to fall upon the drain terminal, causing much higher (). As shown in the Figure 4, the value of is 10 times more than that of . On the contrary, when the DS-TFET is a negative gate bias, is the biggest part of the total capacitance. The gate capacitance of DS-TFET was just slightly increased. This can explain that the dual source regions can increase total capacitance.

Figure 4: Gate-to-drain capacitance and gate-to-source capacitance (a) total gate capacitance (b) with respect to the gate voltage at  V for conventional and DS-TFET.

As shown in Figure 4, rapidly decreases for the further increase in (). When the DS-TFET is forward biased and is greater than threshold voltage , the electron inversion layer becomes thicker for the further increase in , and potential barrier is reduced in channel-to-drain side, so rapidly increases. is the Miller capacitance, when electron concentration is equal to the body doping concentration in the inversion layer, the total number of electrons reaches saturation, and becomes constant. It can be seen clearly in Figure 4 that decreases slightly from the value of the of −0.5 V to 0.5 V, due to the electron inversion blocks the coupling of the gate-to-source capacitance and the source depletion width increases with gate voltage. In particular, is greater than 0 V (), once again decreases, due to the can easily affect the channel-to-source tunnel junction, so the tunnel barrier of channel-to-source side will be more narrow. However, is less than  V, source depletion layer is formed and so does the source charge, and now is much less than . In particular, is smaller than −0.55 V, drops quickly with decreasing (). is very small, due to the presence of the channel-to-drain tunnel barrier. is dominated by the gate and the source depletion width, as shown in Figure 4. These features of capacitance fully demonstrate the symmetry of TFET. We now investigate the influence of on the gate-to-source capacitance and gate-to-drain capacitance. A plot of gate-to-drain capacitance and gate-to-source capacitance as a function of for is shown in Figure 5. For n-type DS-TFET and conventional n-TFET, it is observed that gate-to-source capacitance increases for increasing ; however, the gate-to-drain capacitance drops rapidly at  V. It also indicates in Figure 4 that the capacitance values of DS-TFET are bigger than conventional one; however, they are still the same order of magnitude. It is the same as previous result that two capacitors are connected in parallel. At a fixed , the trends of the and coincide with the foregoing discussion [17, 18]. It is also shown from the capacitance-voltage characteristics at  V and 0.6 V in Figure 5(b) that rapidly decreases for further increase at  V. Meanwhile, the reaches saturation, due to the reduction in the tunnel barrier width for further ; the source depletion width also weakly depends on the drain voltage. will be very small due to higher potential barrier between channel and drain and reduction of the inversion electron concentration in the channel, respectively. On the other hand, increases rapidly before  V, due to the reduction in tunneling barrier for higher . After saturation, continues to increase no longer, because the additional cannot affect the channel-to-drain junction.

Figure 5: (a) Capacitance-voltage characteristics showing the and capacitances as function of at  V for DS n-TFET and conventional n-TFET. (b) Capacitance-voltage characteristics showing the and capacitances as function of for two different values of for DS n-TFET.
3.3. Impact of Scaling

We now research the impact of a varying drain region length on the ambipolar current dependence of the device performance. All other device parameters are kept the same as that in the previous case. For the DS-TFET, the transfer characteristics are shown for four different lengths of the drain region. In order to see the impact of the total length of command drain region on the ambipolar current, the transfer characteristics were shown in Figure 6(a). As shown in Figure 6(a), the leakage current drops, due to an increasing in length of the common drain region. It is evident that a shorter common drain region causes more and larger electrostatic field drop on the channel-to-drain side junction. The now appears across the channel-drain junction, and the geometry enables stronger coupling of gate-to-drain, which results in a higher leakage current. The longer the length of , the less the leakage current.

Figure 6: Transfer characteristics of the DS-TFET: (a) drain-extension dependence; (inset) ambipolar current versus drain region length, where the is the distance from middle to the gate edge; (b) gate-source overlap dependence; (inset) on-state current versus overlap length.

To improve the on-state current for the DS-TFET, the gate-source overlap was adopted. All other device parameters are kept the same as that in the previous case; the gate-source overlap length is only changed. It can be seen in Figure 6(b) that the gate-source overlap length was increased, which resulted in increasing on-state current . It can be explained that vertical tunneling happened in the vertical orientation except for gate-source overlap region, in which is 0 nm.

This implies that the gate electrode would affect not only the channel-source tunneling junction, but also the middle of channel. Not only in lateral direction electrons is tunneling across the tunneling junction, but in vertical direction. Due to these electrons would be far away from the middle of the source region to close to oxide-semiconductor interface. It can be seen clearly in Figure 7 that an increasing in gate-source overlap length resulting in corresponding enlargement of tunneling junction area. The on-state current increases linearly with the tunnel junction area for . When the overlap length reaches 25 nm, the current is dominated totally by vertical band-to-band tunneling (BTBT) current.

Figure 7: Plots showing the eBTBT rates for the DS n-TFET biased at  V and  V for different values of the gate-source overlap. (a) 5-nm overlap length, (b) 10-nm overlap length, (c) 15-nm overlap length, (d) 20 nm overlap length, and (e) 25 nm overlap length.

All the above simulation results also indicate that it is reasonable to experimentally research the DS-TFET geometry since the device performance is easily affected by the gate-source and gate-channel periphery.

3.4. Delay-Power versus Supply Voltage

In Figure 8(a), the simulated gate capacitance is shown as a function of gate voltage at a drain voltage of 0 V. In on-state, the capacitance is dominated by the enhancement Miller capacitance , which mainly comes from inversion charge [18]. The simulated curve is the same as Figure 4. Although the threshold voltages are different, the device capacitance is still less than 17 fF in Figure 8(a). For different work function, there are different threshold voltages, respectively. It is can be seen in Figure 8(b) that the threshold voltages increase since work function is increased, which is consistent with the work function characteristics [19]. From 4.3 eV to 4.6 eV, the values of are 0.23 V, 0.26 V, 0.45 V, and 0.52 V, respectively.

Figure 8: (a) Gate capacitance as a function of gate-to-source voltage for different threshold voltage . (b) Simulated transfer characteristics, for DS-TFET device with varying , where is defined at a gate voltage where the device exhibits a sharp rise in drain current.

Figure 9(a) shows the effects of on the on-state current . The on-state current will be limited by . For a higher DS-TFET, if it operates in threshold region leading to a lower , hence, it is required to apply a larger to achieve a lower delay. The relatively higher threshold voltage leads to a lower leakage current; the lower consumes lesser energy for the operating frequencies <100 MHz. The lower requires a lower for obtaining the same targeted performance leading to quite lower energy dissipation. The extracted delay is shown as a function of supply voltage in Figure 9(b) for the DS-TFET. Roughly delay is given by [20]. Better gives a better performance for a fixed . Figure 8(a) shows that the capacitance magnitude is about 17 fF. DS-TFET delay decreases with decreasing the threshold voltage, due to the on-state current improved at a fixed supply voltage. As shown in Figure 9(c), the dynamic power is roughly calculated by [21, 22]. It can be proved in Figure 9(c) that the lower delay at a fixed results in larger dynamic power dissipation. The static power dissipation can be obtained by , and it can be seen in Figure 9(d) that the higher results in higher static power dissipation. All the device performance has been improved remarkably; the static power dissipation is ≪1 fW. It is necessary to reduce power consumption for a longer battery life. For this purpose, it is shown in Figure 9(e) static energy as a function of maximum operation frequency. Figure 9(e) indicates that static energy will decrease with increasing in the operating frequency. Meanwhile, the curve shows that the smaller the threshold voltage, the less the static energy. For a lower operating and a given , it is import to reduce threshold voltage for a leakage current. For mobile devices, most of the time they are in standby mode where very low signal active and longer battery life are need, so it is necessary to optimize the high devices. Due to very low leakage current, the DS-TFET is fit for the low power circuit at a lower operating frequency and for a fixed .

Figure 9: (a) On-state current at , (b) delay versus supply voltage for DS-TFET devices for different threshold voltage, (c) dynamic power versus supply voltage, (d) static power versus supply voltage, and (e) static energy versus supply voltage maximum frequency.

Figure 10(a) shows the total energy per operation as a function of operating frequencies. The total energy consists of static and dynamic energy. For the lower DS-TFET, on-state current is higher at the lower supply voltage and a lower leakage current, resulting in smaller total energy. In this analysis, the energy per operation of this system is given by [23]where is the number of inverter stages, is a technology-dependent parameter that represents delay degradation due to the slope of the input signal, and is an activity factor. is the leakage current of a single inverter. All other variables are mentioned previously for DS-TFET. The equation reveals that a great deal about the energy depend on and , where , ,  fF, and and are extracted from TCAD simulations. The high threshold voltage requires a higher supply voltage for meeting performance indicators, so the overall dissipation also will be increased.

Figure 10: (a) Total energy operation versus maximum frequency for different threshold voltage ; a low can be used with a lower supply voltage resulting in low energy dissipation; the smallest leads to an energy saving of about 5x in comparison with high at 1 MHz; (b) energy-delay product (EDP) for different . It can be seen that the smallest value of can be optimized compared with other values.

Sometimes it is important to take energy-delay product (EDP) into account for a sufficient level of performance in mobile devices. It can be seen clearly in Figure 10(b) that the highest leads to maximum EDP. Due to higher energy and higher delay, the high is unfit for low power applications. The low is quite superior at lower supply voltages.

3.5. Effect of Variation in Oxide Thickness

It is observed in Figure 11 that the impact of the oxide thickness on the device performance of the DS-TFET and conventional TFET are studied. All other device dimensions and parameters are kept the same as in the previous case. The body thickness is 10 nm, gate length is 45 nm, drain region length  nm, gate-channel underlap is 0 nm, and gate-source overlap is 0 nm. The values of the oxide thickness used are 2 nm, 3 nm, and 4 nm. The effects of varying the value of the oxide thickness on the gate capacitance characteristics of the n-type DS-TFET are shown in Figure 11(a). It is evident in Figure 11(a) that an increase in the value of the oxide thickness results in corresponding reduction of the gate capacitance. Shrinking of the oxide thickness enhances the Miller capacitance effects. The reason for this behavior is improvement ability of gate control over channel, which increases electron concentration in the channel for further . In particular, the carrier concentration is higher at the drain side than source side. The gate-to-drain dominates in on-state while gate-to-source in off-state.

Figure 11: (a) Gate capacitance as a function of for four different values of oxide thickness for DS n-TFET, (b) delay versus supply voltage for DS-TFET and conventional TFET for different oxide thickness, (c) total energy per operation versus the maximum frequency for DS-TFET and conventional TFET corresponding to the same other dimensions and parameters, and (d) EDP versus supply voltage for DS and conventional TFET for three different values of oxide thickness.

In Figure 11(b), the delay curves of the DS and conventional TFET were shown. The delay reduces with increasing oxide thickness, due to thin oxide thickness leading to high current even near off-state condition in DS-TFET at . Figure 11(c) shows that DS-TFET and conventional TFET have three different oxide thickness values. The thinnest oxide thickness produces the relatively higher on-state currents at lower supply voltages and the delay is calculated according to the . So the delay reduced with decreasing the oxide thickness. It can be seen in Figure 11(c) that the slimmest oxide DS-TFET consumes the least energy for operating frequency <100 MHz. The thickest oxide DS-TFET needs a higher supply voltage for the better performance leading to the higher energy dissipation per operation. Figure 11(d) shows the EDP values of three oxide thickness DS-TFET, the thickest oxide device consumes the highest static energy and dynamic energy, and the on-state current is the smallest one of them and the highest delay, resulting in very high EDP.

4. Conclusion

In summary, we have shown that the DS-TFET can improve the on-state current by dual source regions. The increased tunnel junction area leads to improving the on-state current. The drive current of heterojunction DS-TFET can exceed the MOSFET. Although heterojunction DS-TFET will produce a large parasitic capacitance which comes from Miller effect, this disadvantage is not obvious. In contrast, the reduction of EDP and total energy per operation of DS-TFET makes it a strong candidate. An ultra thin thickness of body and oxide also reduces the total energy per operation and EDP. DS-TFET simulations revealed that dual source regions can improve the on-state current and keep the excellent characteristics of the TFET device at the same time.

Conflict of Interests

The authors declare that there is no conflict of interests regarding the publication of this paper.


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