Drive Current Enhancement in TFET by Dual Source Region

Figure 1

(a) Process flow of DS-TFET. (i) Wet chemical etching of oxide layer. (ii) Drain implantation. (iii) Wet chemical etching of oxide layer. (iv) Source implantation. (v) Wet chemical etching and CVD for metal electrode. (v) Spacer formation and gate electrode. (b) Two-dimensional cross section of the simulated device structure for DS-TFET and conventional TFET:  nm,  nm,  nm,  nm,  nm, and  nm.

(a)

(b)