Drive Current Enhancement in TFET by Dual Source Region

Figure 7

Plots showing the eBTBT rates for the DS n-TFET biased at  V and  V for different values of the gate-source overlap. (a) 5-nm overlap length, (b) 10-nm overlap length, (c) 15-nm overlap length, (d) 20 nm overlap length, and (e) 25 nm overlap length.