Table of Contents Author Guidelines Submit a Manuscript
Journal of Electrical and Computer Engineering
Volume 2015, Article ID 905718, 11 pages
http://dx.doi.org/10.1155/2015/905718
Research Article

Drive Current Enhancement in TFET by Dual Source Region

School of Microelectronics, Xidian University, Xi’an 710071, China

Received 9 January 2015; Revised 15 April 2015; Accepted 3 May 2015

Academic Editor: Muhammad Taher Abuelma’atti

Copyright © 2015 Zhi Jiang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

Linked References

  1. International Technology Roadmap for Semiconductors (ITRS), 2011, http://www.itrs.net/.
  2. A. M. Ionescu and H. Riel, “Tunnel field-effect transistors as energy-efficient electronic switches,” Nature, vol. 479, no. 7373, pp. 329–337, 2011. View at Publisher · View at Google Scholar · View at Scopus
  3. W. Y. Choi, B. G. Park, J. D. Lee, and T. J. K. Liu, “Tunneling field-effect transistors (TFETs) with subthreshold swing (SS) less than 60 mV/dec,” IEEE Electron Device Letters, vol. 28, no. 8, pp. 743–745, 2007. View at Publisher · View at Google Scholar · View at Scopus
  4. T. S. Arun Samuel, N. B. Balamurugan, S. Bhuvaneswari, D. Sharmila, and K. Padmapriya, “Analytical modelling and simulation of single-gate SOI TFET for low-power applications,” International Journal of Electronics, vol. 101, no. 6, pp. 779–788, 2014. View at Publisher · View at Google Scholar · View at Scopus
  5. A. Guo, P. Matheu, and T.-J. K. Liu, “SOI TFET ION/IOFF enhancement via back biasing,” IEEE Transactions on Electron Devices, vol. 58, no. 10, pp. 3283–3285, 2011. View at Publisher · View at Google Scholar
  6. F. Mayer, C. Le Royer, J.-F. Damlencourt et al., “Impact of SOI, Si1-xGexOI and GeOI substrates on CMOS compatible tunnel FET performance,” in Proceedings of the IEEE International Electron Devices Meeting (IEDM '08), pp. 1–5, December 2008. View at Publisher · View at Google Scholar · View at Scopus
  7. E.-H. Toh, G. H. Wang, G. Samudra, and Y.-C. Yeo, “Device physics and design of double-gate tunneling field-effect transistor by silicon film thickness optimization,” Applied Physics Letters, vol. 90, no. 26, Article ID 263507, 2007. View at Publisher · View at Google Scholar · View at Scopus
  8. J. Zhang, J. He, X. Zhou et al., “A unified charge-based model for SOI MOSFETs applicable from intrinsic to heavily doped channel,” Chinese Physics B, vol. 21, no. 4, Article ID 047303, 2012. View at Publisher · View at Google Scholar
  9. P. Guo, Y. Yang, Y. Cheng et al., “Tunneling field-effect transistor with Ge/In0.53Ga0.47As heterostructure as tunneling junction,” Journal of Applied Physics, vol. 113, no. 9, Article ID 094502, 10 pages, 2013. View at Publisher · View at Google Scholar · View at Scopus
  10. N. D. Chienand and L. T. Vinh, “Drive current enhancement in tunnel field-effect transistors by graded heterojunction approach,” Journal of Applied Physics, vol. 114, no. 9, Article ID 094507, 2013. View at Publisher · View at Google Scholar
  11. Y. Lu, G. Zhou, R. Li et al., “Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned,” IEEE Electron Device Letters, vol. 33, no. 5, pp. 655–657, 2012. View at Publisher · View at Google Scholar · View at Scopus
  12. K. K. Bhuwalka, J. Schulze, and I. Eisele, “Performance enhancement of vertical tunnel field-effect transistor with SiGe in the δp+ layer,” Japanese Journal of Applied Physics, vol. 43, no. 7, pp. 4073–4078, 2004. View at Publisher · View at Google Scholar · View at Scopus
  13. A. C. Ford, C. W. Yeung, S. Chuang et al., “Ultrathin body InAs tunneling field-effect transistors on Si substrates,” Applied Physics Letters, vol. 98, no. 11, Article ID 113105, 2011. View at Publisher · View at Google Scholar · View at Scopus
  14. Y. Lu, G. Zhou, R. Li et al., “Performance of AlGaSb/InAs TFETs with gate electric field and tunneling direction aligned,” IEEE Electron Device Letters, vol. 33, no. 5, pp. 655–657, 2012. View at Publisher · View at Google Scholar · View at Scopus
  15. T. Nowozin, A. Wiengarten, L. Bonato et al., “Electronic properties and density of states of self-assembled GaSb/GaAs quantum dots,” Journal of Nanotechnology, vol. 2013, Article ID 302647, 5 pages, 2013. View at Publisher · View at Google Scholar · View at Scopus
  16. B. Rajamohanan, D. Mohata, A. Ali, and S. Datta, “Insight into the output characteristics of III-V tunneling field effect transistors,” Applied Physics Letters, vol. 102, no. 9, Article ID 092105, 2013. View at Publisher · View at Google Scholar · View at Scopus
  17. C. Alper, L. De Michielis, N. Daǧtekin, L. Lattanzio, D. Bouvet, and A. M. Ionescu, “Tunnel FET with non-uniform gate capacitance for improved device and circuit level performance,” Solid-State Electronics, vol. 84, pp. 205–210, 2013. View at Publisher · View at Google Scholar · View at Scopus
  18. S. Mookerjea and R. Krishnan, “On enhanced Miller capacitance effect in interband tunnel transistors,” IEEE Transactions on Electron Devices, vol. 30, no. 10, pp. 1102–1104, 2009. View at Google Scholar
  19. A. S. Verhulst, W. G. Vandenberghe, K. Maex, S. De Gendt, M. M. Heyns, and G. Groeseneken, “Complementary silicon-based heterostructure tunnel-FETs with high tunnel rates,” IEEE Electron Device Letters, vol. 29, no. 12, pp. 1398–1401, 2008. View at Publisher · View at Google Scholar · View at Scopus
  20. P.-F. Wang, K. Hilsenbeck, T. Nirschl et al., “Complementary tunneling transistor for low power application,” Solid-State Electronics, vol. 48, no. 12, pp. 2281–2286, 2004. View at Publisher · View at Google Scholar · View at Scopus
  21. S. Hanson, B. Zhai, K. Bernstein et al., “Ultralow-voltage minimum-energy CMOS,” IBM Journal of Research and Development, vol. 50, no. 4-5, pp. 469–490, 2006. View at Publisher · View at Google Scholar · View at Scopus
  22. H. Madan, V. Saripalli, H. Liu, and S. Datta, “Asymmetric tunnel field-effect transistors as frequency multipliers,” IEEE Electron Device Letters, vol. 33, no. 11, pp. 1547–1549, 2012. View at Publisher · View at Google Scholar · View at Scopus
  23. A. Rajoriya, M. Shrivastava, H. Gossner, T. Schulz, and V. R. Rao, “Sub 0.5 v operation of performance driven mobile systems based on area scaled tunnel FET devices,” IEEE Transactions on Electron Devices, vol. 60, no. 8, pp. 2626–2633, 2013. View at Publisher · View at Google Scholar · View at Scopus