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Journal of Electrical and Computer Engineering
Volume 2015, Article ID 915409, 10 pages
Research Article

Hybrid Model: An Efficient Symmetric Multiprocessor Reference Model

1Department of Information Science and Electronic Engineering, Zhejiang University, Hangzhou 310027, China
2Institute of VLSI Design, Zhejiang University, Hangzhou 310027, China

Received 23 September 2014; Revised 26 January 2015; Accepted 15 March 2015

Academic Editor: Marco Platzner

Copyright © 2015 Shupeng Wang et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


Functional verification has become one of the main bottlenecks in the cost-effective design of embedded systems, particularly for symmetric multiprocessors. It is estimated that verification in its entirety accounts for up to 60% of design resources, including duration, computer resources, and total personnel. Simulation-based verification is a long-standing approach used to locate design errors in the symmetric multiprocessor verification. The greatest challenge of simulation-based verification is the creation of the reference model of the symmetric multiprocessor. In this paper, we propose an efficient symmetric multiprocessor reference model, Hybrid Model, written with SystemC. SystemC can provide a high-level simulation environment and is faster than the traditional hardware description languages. Hybrid Model has been implemented in an efficient 32-bit symmetric multiprocessor verification. Experimental results show our proposed model is a fast, accurate, and efficient symmetric multiprocessor reference model and it is able to help designers to locate design errors easily and accurately.