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Journal of Electrical and Computer Engineering
Volume 2015, Article ID 939028, 10 pages
http://dx.doi.org/10.1155/2015/939028
Research Article

A Formal Verification Methodology for DDD Mode Pacemaker Control Programs

Department of Electrical and Computer Engineering, North Dakota State University, 1411 Centennial Boulevard, Fargo, ND 58102, USA

Received 1 June 2015; Revised 4 August 2015; Accepted 12 August 2015

Academic Editor: Massimo Poncino

Copyright © 2015 Sana Shuja et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.

How to Cite this Article

Sana Shuja, Sudarshan K. Srinivasan, Shaista Jabeen, and Dharmakeerthi Nawarathna, “A Formal Verification Methodology for DDD Mode Pacemaker Control Programs,” Journal of Electrical and Computer Engineering, vol. 2015, Article ID 939028, 10 pages, 2015. https://doi.org/10.1155/2015/939028.