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Journal of Electrical and Computer Engineering
Volume 2016, Article ID 4237350, 27 pages
Research Article

Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

1POLCOMING, Information Engineering Unit, University of Sassari, Sassari, Italy
2Department of Electrical and Electronic Engineering (DIEE), University of Cagliari, Cagliari, Italy

Received 18 April 2016; Accepted 14 September 2016

Academic Editor: Wen B. Jone

Copyright © 2016 Francesca Palumbo et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This paper focuses on how to efficiently reduce power consumption in coarse-grained reconfigurable designs, to allow their effective adoption in heterogeneous architectures supporting and accelerating complex and highly variable multifunctional applications. We propose a design flow for this kind of architectures that, besides their automatic customization, is also capable of determining their optimal power management support. Power and clock gating implementation costs are estimated in advance, before their physical implementation, on the basis of the functional, technological, and architectural parameters of the baseline design. Experimental results, on 90 and 45 nm CMOS technologies, demonstrate that the proposed approach guides the designer towards optimal implementation.