Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Table 15

FFT use case at 90 nm CMOS technology: power gating overhead estimation step accuracy, using reports generated without the real switching activity.

LR	PG overhead%
	Est.	Real	Err.%
	−30.54	−26.10	17.07
	−0.19	−1,99	90.22
	−21.83	−6.95	214.30
	−0.12	−0.67	80.97
	−0.06	−0.59	90.11
	−0.07	0.56	86.60
	−15.39	−2.64	482.93
	−0.38	−0.02	1941.81