Modelling and Automated Implementation of Optimal Power Saving Strategies in Coarse-Grained Reconfigurable Architectures

Table 5

FFT use case: features of the different configurations integrated on the CGR design. Data refer to a 90 nm CMOS target technology.

FFT configuration		LRs	Area%	Static [nW]	Internal [nW]
	0.42	(2, 6, 8)	12.86	1750407	1307259
	0.21	(2, 5, 7, 8)	20.81	1752106	1539855
	0.04	(2, 3, 4, 7)	35.28	1757485	2020953
	0.33	(1, 3, 7, 8)	98.03	1776056	2411257