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Journal of Electrical and Computer Engineering
Volume 2016 (2016), Article ID 8202581, 9 pages
Research Article

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Faculty of Engineering, Shahrekord University, Shahrekord 8818634141, Iran

Received 6 April 2016; Accepted 17 August 2016

Academic Editor: M. Jamal Deen

Copyright © 2016 Noushin Ghaderi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.

1. Introduction

The role of a phase-locked loop or a delay-locked loop (DLL) is to generate a clock signal which is usually a multiple of a reference clock and is synchronized with the reference clock in phase. They are extensively utilized in many applications including clock data recovery systems and frequency synthesis circuits.

One of the most important components of the PLL and DLL, which is often considered as the bottleneck, is the phase frequency detector (PFD). The limited speed of this block is the main limiting factor in the data rate of the PLL. In high frequencies, the PFDs cannot follow the phase differences between reference and feedback clocks. Therefore, a frequency divider circuit is often inserted before the PFD block in the feedback path of the PLL. It means that the input clock frequency of the PFD is reduced. However, by adding the divider circuit, the overall jitter of the PLL will extremely increase. Thus, by designing a high frequency PFD, the divider circuit will be omitted and the noise behavior of the PLL will be improved [1].

Another important component of the PLL is charge pump circuit‎. It converts the output signal of PFD into an accurate amount of current‎. ‎In practice‎, there are some ‎nonidealities in the charge pump circuit. Reference spurs and phase offset are due to the current mismatch while the variations of the PLL loop bandwidth are caused by the variations of the output current amplitude. If the current matching and control voltage range of a charge pump circuit increase simultaneously, then the locking range frequency of the PLL will increase considerably.

In this paper a wide dynamic output voltage range, high impedance, and low power charge pump based on a novel bulk driven Wilson current mirror is presented. Some optimization algorithms are employed to improve the efficiency of the circuit.

2. Proposed PFD

The PFDs detect a phase error signal which is passed through a loop filter to control the delay of a controllable delay line. Therefore, in addition to determination of accuracy, a PD plays a key role in the speed and efficiency of PLL’s performance.

A closed loop is the general structure used in the PFD because it is simple, easy to implement, and immune to the dead-zone problem. Because of the feedback path, however, it has a limited speed which confines its usage in high speed circuits. Furthermore, some rising edges can be missed in the detection when the edges are overlapped with the reset signal [2]. Till now many circuits have been suggested to make the feedback path faster [36]; however the feedback path still remains in all of them which causes a reduction in the speed.

Authors in [7] proposed an open loop PD to achieve a high speed performance, without the issue of the reset signal. However, the PFD circuit tends to dissipate crowbar current when both input signals are high. It means that the circuit has some extra average DC power consumption.

The proposed circuit with a very simple structure solves the above problem. Furthermore, the proposed circuit solves the dead-zone and missing edge problems completely.

The task of a PD circuit is to compare the rising edge of two inputs ( and in Figure 1) and generate a signal which is set to a high value with the rising edge of the first input and then is reset to a low value with the rising edge of the second one.

Figure 1: Proposed PD: (a) Up path. (b) Down path. (c) The waveforms of the PD when leads ; (d) when lags .

Figures 1(a) and 1(b) show the proposed PD, for Up and Down paths, which indicate two symmetrical and very simple circuits for Up and Down signals. The waveforms of the PD are shown in Figures 1(c) and 1(d). In Figure 1(c), leads . If initially and = , then a rising transition on leads to charge the output capacitor through . Therefore, the Up output node will be set to the high value. The Up node stays in this state until rising transition on . On the other hand, at the Down circuit with at the high value, the transistor will be on, keeping the down output at the low value. After the rising transition on , will turn on, causing the capacitor to discharge to the ground. Therefore, when returns to the low value and turns off, Down output will remain at zero value. The circuits operate in the opposite manner when lags (Figure 1(d)).

As can be observed, the above circuit is extremely simple and fast. Furthermore, due to the use of only three transistors in each path, the power consumption is considerably low. But the proposed PD still suffers from the following problems.

The first problem is as follows: Since the parasitic capacitance of node is smaller than the parasitic capacitance of the output node, the output node will not be charged through this node completely. Adding an additional capacitor to the node will add some problems such as extra chip area and longer rise and fall time.

The second problem is its dead-zone problem. This problem may occur when the inputs have a very small phase difference. Therefore, the output pulse may not find enough time to turn on the charge pump switches. To overcome the above two problems, the proposed PD is modified as shown in Figure 2, in which and are delayed waveforms of and signals. The ideal waveforms of two outputs are also shown in this figure.

Figure 2: Modified PD: (a) Up path. (b) Down path. (c) The ideal waveforms of the modified PD when leads ; (d) when lags .

Circuit performance is as follows: by delaying and signals on gates of , , and , the zero value of “up” signal will occur a few seconds later. As a result, a high level of “up” signal will become wider than the real amount and the phase difference will be shown more extensive than the actual value. This amount of broadness must be equal to the precharging time () of the internal parasitic capacitances.

In Figure 2(c), leads . As can be seen, just after the rising transition on , signal will be set to the high value while , which is the delayed waveform of signal, still remains at the low value. Therefore, and turn on and the Up output will be set to the high value. In the same way, just after the rising transition on , and turn on, consequently setting the Down output to the high value. With rising transition on , both of the Up and Down outputs return to the low value. The circuits operate in the opposite manner when lags as shown in Figure 2(d).

According to [19], the time which is taken by the signal to change from low (high) value to 70% (30%) of high (low) value of logic states is called the gate rise time (or fall time). In this circuit, rise time and fall time make .

The sum of output rise time and fall time is calculated to estimate the maximum operational frequency of the proposed PFD.where τ is considered as time constant, is the equivalent resistant of the charging or discharging path at the output node (UP or DN), is the output equivalent capacitance, is the delay gate, and is the Not gate equivalent capacitances.

By calculating the above equations, is obtained as 48.33 ps. Figure 3 shows that the dead zone is compensated by delay gates through the Not gate and precharging time. and are delay times caused by Not gate and delay gate, respectively. The values of and are obtained as 64.43 ps and 16.1 ps, respectively. It means that the dead zone is entirely removed.

Figure 3: The realistic waveforms of the modified PD.

It is evident that the delay time in Figure 3 cannot exceed the value of 3/4 of the clock pulse width. Therefore, the minimum value of pulse width is 85.9 ps. As a result, the maximum frequency of the proposed PFD is obtained as 5.82 GHz.

The proposed PD is simulated in 0.18 μm CMOS technology by HSPICE software using level 49 parameters. The results are drawn in Figure 4 using MATLAB software. The figure shows the difference between average values of Up and Down signals versus the phase difference of two inputs at six different frequencies, 1–100 MHz, 1 GHz, 3 GHz, 4 GHz, and 5 GHz. Since the nonlinearity of the characteristic at the high frequency happens at large phase differences, where the polarity is more important than the magnitude, this nonlinearity can be ignored. The diagram should be linear in small phase differences to minimize the locking time jitter of the PLL. The region around zero phase difference shows the accuracy of the PFD even at 5 GHz frequency. The power consumption of the proposed PD at 5 GHz frequency is about 0.3 mW. Table 1 summarizes these results and presents a performance comparison among this work and others.

Table 1: Performance comparison of the proposed phase detector.
Figure 4: Difference between average values of Up and Down signals versus the phase difference of two inputs.

3. Proposed Charge Pump Circuit

One of the most important components of the PLL is the charge pump circuit‎. An adaptive body bias charge pump circuit is proposed in [11]‎. In this circuit a number of resistances are used to compensate current variation‎. ‎However, multiple parameters, such as temperature and fabrication, change the value of these resistances ‎and are not reliable. The charge pump presented in [12] has used a compensation method to reach a high output swing. However the circuit structure is complicated. Moreover, in this circuit the power supply and hence the power consumption are placed high to achieve a high output swing. In order to increase the output voltage swing of the charge pump, in [13] a bulk driven method in a cascade structure has been used. However, using a cascade structure sets limitation to output swing.

‎A novel bulk driven‎, ‎low voltage charge pump for high performance PLLs is proposed in this paper‎. This charge pump is designed based on Wilson current mirror by a novel bulk driven method. Output resistance and output swing are increased simultaneously.

The charge pump circuits‎ must be designed to have ‎a high output swing. However, there are some limitations in output swing, especially when transistors are placed in cascade form‎, to obtain the high output impedance. To overcome the above problem, bulk driven technique is employed in the proposed circuit. The proposed charge pump circuit is designed based on Figure 5. This circuit is a modified version of a super-Wilson current mirror [20]. As can be seen, the diode connection transistor of an ordinary circuit is replaced with a cascade one. Therefore, the loop gain is increased by a factor of .

Figure 5: Proposed high swing Wilson current mirror.

The proposed charge pump circuit is indicated in Figure 6. In this circuit s and s which are controlled by DN and UPb, respectively, act as charge pump switches. s and s are working for faster and better switching. When these MOSFETs turned on, the gate’s capacitor of or will be discharged and turn off faster.

Figure 6: Proposed charge pump circuit.

In the proposed circuit ()–() are used to connect the bulk terminals of () and () to a higher voltage in comparison with the circuit of Figure 5. It means that the source-bulk voltage () is decreased. Therefore, according to (3), the threshold voltage () is reduced too. Equations (4) and (5) indicate that, by decreasing , and are increased and is decreased.In (6), by increasing and and decreasing and , the output voltage swing is extremely increased.Output resistance is equal toOne of the most important issues in bulk driven circuits is nonideal behavior of the MOSFETs due to their channel formations. ‎The operation of the bulk driven MOSFET is similar to a Junction Field Effect Transistor (JFET)‎. Because of nonlinear mathematical equations of the MOSFETs at low voltages, analysis of the circuit becomes complicated. For solving this problem, designers have compensated these nonidealities by choosing the aspect ratios of MOSFETs by trial and error (T&E) method [21]. Using of this method has been the only solution so far. In this paper in addition to T&E, MATLAB software is used to apply two methods of optimization algorithms to find the optimum aspect ratios. The main purpose is equalizing the charge and discharge current in a wide output voltage range to achieve the highest output current matching.

4. Tuning by Particle Swarm Optimization and Genetic Algorithm

In this paper, in addition to T&E, MATLAB software is used to apply two methods of optimization algorithms to find the optimum aspect ratios. The main purpose is to equalize the charge and discharge current in a wide output voltage range to achieve the highest output current matching.

To optimize the aspect ratios of M4nM9n and M4pM9p and choose the best values, Particle Swarm Optimization (PSO) and Genetic Algorithm (GA) are used.

4.1. Particle Swarm Optimization

Particle Swarm Optimization (PSO) was introduced in 1995 by Kennedy and Eberhart [22]. In PSO algorithm, a random population of points is generated. Each point represents a member of the population. In PSO algorithm, there is no sudden jump or confusion; each point is a solution. Considering and as particle position and velocity, respectively, the position of th particle in a space with dime is represented with .

The position of each particle is changed at the next stage and it reaches a new position. The best position of th particle which corresponds to the lowest cost function for that particle is saved in . In addition, of all particles are compared and the position of particle which has the lowest cost function is saved in . The next vector of each particle depends on its position and its distance to its and its distance to . The relations of particles movements are as follows:where indicates a parameter that prevents going out of suitable search space which causes the solution to be in acceptable region; and are constants which represent the speed of learning or pulling to and , and the weighing function is given bywhere and indicate the minimum and maximum weighing functions and iter denotes the number of iterations.

In order to optimize the parameters of the controller by PSO, the following cost function is used:where is the final time of simulation, is the error signal, and is the settling time of the system.

4.2. Genetic Algorithm

Genetic Algorithm is a search-based optimization method [23]. This algorithm has been proposed by John Holland (1962). In the algorithm, he has benefited from two principles of selection and reproduction in the nature. Genetic Algorithm can be considered as an oriented random optimization method which gradually moves towards optimal point.

Unlike other common optimization models in which only one point is used in each stage of optimization process, in Genetic Algorithm, a group of points are used.

If our optimization target function is asthen, the objective is to find the value of in such a way that function has the minimum value. In Genetic Algorithm, at the first stage, a set of chromosomes are randomly created (random strings from to ). These refer to genes. Putting each of these chromosomes in target function, the value of function is obtained. The first generation concludes through appropriate scoring to these values. The first generation is called parents generation.

The process of creating offspring (children) in the next generations follows the following three general principles:(a)Crossover(b)Elite(c)Mutation.After the second generation and after creating offspring with ratios determined by selection algorithms, new generation children are selected. Putting these children into target function and scoring them, then, the algorithm is reiterated until the algorithm meets the ending criteria (such as the number of generation and time), causing the algorithm to be stopped.

4.3. Results Optimization

In this study, the values of transistors aspect ratio are optimized using the following considerations.

It should be noted that aspect ratios of () equal (), () equal (), and () equal (). The aspect ratios of the MOSFETs should be positive.

In the present study, the number of the algorithm iterations is the stopping criterion. Both PSO and GA are simulated using the following two sets of parameters:(a)parameters iteration = 100 and population = 30,(b)parameters iteration = 200 and population = 50.The results pertained to the target function optimization of (10) have been shown in Figures 7 and 8. The respective figures, in fact, indicate cost function improvement for the increase in the number of iterations.

Figure 7: Convergence objective function for Genetic Algorithm.
Figure 8: Convergence objective function for Particle Swarm Optimization.

The results of T&E and optimal value factor’s aspect ratios are presented in Table 2.

Table 2: Aspect ratio values of MOSFETs at different methods.

To verify the efficiency of the proposed circuit, it is simulated under the power supply of 1.8 V in 180 nm CMOS technology using Hspice.‎ Input current is set to 20 μA. Figure 9 shows the charge and discharge output currents of the proposed charge pump which are obtained from T&E, PSO, and GA methods as the output voltage is swept from 0 to 1.8 V‎. As can be seen, the output dynamic voltage ranges of output current matching are 0.25–1.6 V, 0.1–1.65 V, and 0.08–1.65 V for T&E, PSO, and GA, respectively. According to these results, the GA method makes a better performance to this charge pump. Therefore, the aspect ratios which are presented by the GA are chosen for applying to the proposed charge pump. Current mismatch is less than 1% of nominal output current ( or ) over the output range of these methods.

Figure 9: Matching characteristic of the proposed charge pump.

In the usual bulk driven current mirror, the gate terminals are tied to [24]. However, in these circuits, the output current cannot track the input current in a specified range [13]. Figure 10 shows the variations of output current versus input current in the proposed circuit‎. ‎As can be seen, ‎the output current can track the input current in a wide input current range. The overall power consumption of the proposed charge pump circuit is around 160 μW. Table 3 summarizes the performance of the proposed charge pump and compares them with recent publications. As can be observed, the proposed circuit has an excellent voltage swing per , while its power consumption is reasonable.

Table 3: Performance comparison of the proposed charge pump.
Figure 10: Input and output current transfer characteristics.

5. Simulation Results of Proposed PLL

The PLL is designed using the proposed PFD and charge pump circuits. Furthermore, it employs a two-stage voltage controlled ring oscillator [18]. This PLL has a wide locking range from 500 MHz to 5 GHz.

Jitter histogram and eye diagram at 3 GHz operating frequency are depicted in Figure 11, which shows around 0.671 ps and 3.46 ps RMS and peak-to-peak jitters, respectively.

Figure 11: (a) Output jitter histogram at 3 GHz. (b) Output jitter eye diagram at 3 GHz.

Figure 12 shows the output spectrum simulated at 3 GHz. The simulation result shows a reference spur of −72 dBm with a 1.85 GHz frequency offset. The phase noise of the PLL at the locking frequency in different frequency offsets is presented in Figure 13. The output phase noise is −117.6 dBc/Hz at a 1 MHz frequency offset. The total power consumption is about 11.5 mW. The figure of merit of the proposed PLL according to (12) [25] is −198.47 dBc/Hz.where is phase noise, is certain frequency offset, is center frequency, is the power dissipation, and FTR is tuning range of oscillation frequency.

Figure 12: Output spectrum of the VCO.
Figure 13: Simulated phase noise at 3 GHz for different frequency offsets.

Table 4 summarizes these results and presents a performance comparison of this work with some recent papers. The proposed PLL achieves lowest by using a fast PFD circuit and omitting the divider circuit.

Table 4: A performance comparison of proposed circuit with some recent papers.

6. Conclusion

A very simple, low power, high speed, and open loop phase detector is proposed which operates in a wide frequency range from 1 MHz to 5 GHz. Due to the extra simplicity of the circuit, the power consumption is very low and is about 0.3 mW at the highest operational frequency. The dead-zone and missing edge problems are solved completely in the proposed architecture. A high output impedance‎, ‎low power, and single-ended charge pump based on a bulk driven Wilson current mirror‎, ‎with excellent output current matching, is also introduced in this paper. The proposed charge pump aspect ratios parameter was optimized by PSO and GA. Therefore, the dynamic voltage range was increased significantly which is obtained about 88% of power supply. The current mismatch between charge and discharge current is less than 1% of nominal output current. Therefore, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly. However, since a single ended charge pump architecture has a higher substrate and supply noise coupling, a differential charge pump circuit can be considered as a future work. Moreover, the operating frequency range can be increased by tracking the self-oscillation frequencies of the voltage-controlled oscillator and the frequency divider. The rms and peak-to-peak jitters of this PLL at 3 GHz are 0.671 and 3.46 ps, respectively.

Competing Interests

The authors declare that they have no competing interests.


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