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Journal of Electrical and Computer Engineering
Volume 2016, Article ID 8202581, 9 pages
Research Article

A Low Noise, Low Power Phase-Locked Loop, Using Optimization Methods

Faculty of Engineering, Shahrekord University, Shahrekord 8818634141, Iran

Received 6 April 2016; Accepted 17 August 2016

Academic Editor: M. Jamal Deen

Copyright © 2016 Noushin Ghaderi et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


A divider-less, low power, and low jitter phase-locked loop (PLL) is presented in this paper. An extra simple open loop phase frequency detector (PFD) is proposed which reduces the power consumption and increases the overall speed. A novel bulk driven Wilson charge pump circuit, whose performance is enhanced by some optimization algorithms, is also introduced to get high output swing and high current matching. The designed PLL is utilized in a CMOS process with a 1.8 V power supply. It has a wide locking range frequency of 500 MHz to 5 GHz. In addition, through the use of a dead-zone-less PFD and a divider-less PLL, the overall jitter is decreased significantly.