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Journal of Electrical and Computer Engineering
Volume 2017 (2017), Article ID 8207104, 11 pages
Research Article

On Improving the Performance of Dynamic DCVSL Circuits

1Department of Electronics and Communication Engineering, Delhi Technological University, Delhi, India
2Department of Electronics and Communication Engineering, Bharati Vidyapeeth’s College of Engineering, Delhi, India

Correspondence should be addressed to Neeta Pandey

Received 31 July 2016; Revised 18 February 2017; Accepted 20 March 2017; Published 4 April 2017

Academic Editor: Ephraim Suhir

Copyright © 2017 Pratibha Bajpai et al. This is an open access article distributed under the Creative Commons Attribution License, which permits unrestricted use, distribution, and reproduction in any medium, provided the original work is properly cited.


This contribution aims at improving the performance of Dynamic Differential Cascode Voltage Switch Logic (Dy-DCVSL) and Enhanced Dynamic Differential Cascode Voltage Switch Logic (EDCVSL) and suggests three architectures for the same. The first architecture uses transmission gates (TG) to reduce the logic tree depth and width, which results in speed improvement. As leakage is a dominant issue in lower technology nodes, the second architecture is proposed by adapting the leakage control technique (LECTOR) in Dy-DCVSL and EDCVSL. The third proposed architecture combines features of both the first and the second architectures. The operation of the proposed architectures has been verified through extensive simulations with different CMOS submicron technology nodes (90 nm, 65 nm, and 45 nm). The delay of the gates based on the first architecture remains almost the same for different functionalities. It is also observed that Dy-DCVSL gates are 1.6 to 1.4 times faster than their conventional counterpart. The gates based on the second architecture show a maximum of 74.3% leakage power reduction. Also, it is observed that the percentage of reduction in leakage power increases with technology scaling. Lastly, the gates based on the third architecture achieve similar leakage power reduction values to the second one but are not able to exhibit the same speed advantage as achieved with the first architecture.