On Improving the Performance of Dynamic DCVSL Circuits

Table 1

Summary of delay results (ps).

Gate	Style
	Dy-DCVSL	EDCVSL	Dy-TG-DCVSL	TG-EDCVSL
AND-NAND2	500	480	350	340
AND-NAND3	570	530	355	345
XOR-XNOR2	500	480	350	341
XOR-XNOR3	550	490	355	345