On Improving the Performance of Dynamic DCVSL Circuits

Table 2

Leakage power (nW) for the conventional Dy-DCVSL, EDCVSL-LCT and PA-2 Dy-DCVSL-LCT, EDCVSL-LCT based XOR-XNOR2 gate topologies.

Inputs		Architecture
		Conventional		PA-2		Reduction with respect to conventional (%)
A	B	Dy-DCVSL	EDCVSL	Dy-DCVSL-LCT	EDCVSL-LCT	Dy-DCVSL-LCT	EDCVSL-LCT
90 nm node
0	0	9.27	8.9	4.02	4.06	56.6	54
0	1	0.23	0.21	0.16	0.14	30.4	33
1	0	0.23	0.21	0.16	0.14	30.4	33
1	1	9.27	8.9	4.02	4.06	56.6	54
65 nm node
0	0	12.9	12.88	5.16	5	60	61
0	1	0.41	0.27	0.27	0.18	32.2	33.3
1	0	0.41	0.27	0.27	0.18	32.2	33.3
1	1	12.9	12.88	5.16	5	60	61
45 nm node
0	0	22.48	22.48	5.79	5.79	74	74.3
0	1	0.41	0.28	0.28	0.18	33.8	35.7
1	0	0.41	0.28	0.28	0.18	33.8	35.7
1	1	22.48	22.48	5.79	5.79	74	74.3