Research Article

On Improving the Performance of Dynamic DCVSL Circuits

Table 3

Leakage power (nW) for TG-EDCVSL and TG-EDCVSL-LCT based XOR-XNOR2 gate topologies.

InputsArchitecture
ABTG-EDCVSLTG-EDCVSL-LCTReduction with respect to TG-EDCVSL (%)

90 nm node
008.8455
010.180.1327
100.180.1327
118.8455

65 nm node
0012.7561
010.20.1430
100.20.1430
1112.7561

45 nm node
0022.245.774.3
010.210.1338
100.210.1338
1122.245.774.3