Research Article
On Improving the Performance of Dynamic DCVSL Circuits
Table 3
Leakage power (nW) for TG-EDCVSL and TG-EDCVSL-LCT based XOR-XNOR2 gate topologies.
| Inputs | Architecture | A | B | TG-EDCVSL | TG-EDCVSL-LCT | Reduction with respect to TG-EDCVSL (%) |
| 90 nm node | 0 | 0 | 8.8 | 4 | 55 | 0 | 1 | 0.18 | 0.13 | 27 | 1 | 0 | 0.18 | 0.13 | 27 | 1 | 1 | 8.8 | 4 | 55 |
| 65 nm node | 0 | 0 | 12.7 | 5 | 61 | 0 | 1 | 0.2 | 0.14 | 30 | 1 | 0 | 0.2 | 0.14 | 30 | 1 | 1 | 12.7 | 5 | 61 |
| 45 nm node | 0 | 0 | 22.24 | 5.7 | 74.3 | 0 | 1 | 0.21 | 0.13 | 38 | 1 | 0 | 0.21 | 0.13 | 38 | 1 | 1 | 22.24 | 5.7 | 74.3 |
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