Journal of Electrical and Computer Engineering / 2018 / Article / Fig 13

Research Article

Improved Design of Bit Synchronization Clock Extraction in Digital Communication System

Figure 13

System simulated results without digital filter. CLK_LOCAL: the local clock, INSIGNAL: the input signal, Syn_Clock: the synchronization clock, Deduct: the leading control pulse of PD, Add: the lagging control pulse of PD, and Before_Dvf: control module output/frequency divider input.